arm_A15_1: GEL Output: **************************************************************************************************************** arm_A15_1: GEL Output: ***************** DDR3A Leveling Errors ********************* arm_A15_1: GEL Output: PGSR0[27]: WEERR has ** No Error ** arm_A15_1: GEL Output: PGSR0[26]: REERR has ** No Error ** arm_A15_1: GEL Output: PGSR0[25]: WDERR has ** No Error ** arm_A15_1: GEL Output: PGSR0[24]: RDERR has ** No Error ** arm_A15_1: GEL Output: PGSR0[23]: WLAERR has ** No Error ** arm_A15_1: GEL Output: PGSR0[22]: QSGERR has ** No Error ** arm_A15_1: GEL Output: PGSR0[21]: WLERR has ** No Error ** arm_A15_1: GEL Output: PGSR0[20]: ZCERR has ** No Error ** arm_A15_1: GEL Output: PGSR0[11]: WEDONE is ** Set ** arm_A15_1: GEL Output: PGSR0[10]: REDONE is ** Set ** arm_A15_1: GEL Output: PGSR0[9]: WDDONE is ** Set ** arm_A15_1: GEL Output: PGSR0[8]: RDDONE is ** Set ** arm_A15_1: GEL Output: PGSR0[7]: WLADONE is ** Set ** arm_A15_1: GEL Output: PGSR0[6]: QSGDONE is ** Set ** arm_A15_1: GEL Output: PGSR0[5]: WLDONE is ** Set ** arm_A15_1: GEL Output: PGSR0[4]: DIDONE is ** Set ** arm_A15_1: GEL Output: PGSR0[3]: ZCDONE is ** Set ** arm_A15_1: GEL Output: PGSR0[2]: DCDONE is ** Set ** arm_A15_1: GEL Output: PGSR0[1]: PLDONE is ** Set ** arm_A15_1: GEL Output: PGSR0[0]: IDONE is ** Set ** arm_A15_1: GEL Output: ******************************************************** arm_A15_1: GEL Output: Leveling Errors by Byte Lane: arm_A15_1: GEL Output: Byte Lane 0: arm_A15_1: GEL Output: DX0GSR2[6]: WEERR has ** No Error ** arm_A15_1: GEL Output: DX0GSR2[4]: REERR has ** No Error ** arm_A15_1: GEL Output: DX0GSR2[2]: WDERR has ** No Error ** arm_A15_1: GEL Output: DX0GSR2[0]: RDERR has ** No Error ** arm_A15_1: GEL Output: DX0GSR0[25]: QSGERR on Rank1 has ** No Error ** arm_A15_1: GEL Output: DX0GSR0[24]: QSGERR on Rank0 has ** No Error ** arm_A15_1: GEL Output: DX0GSR0[6]: WLERR has ** No Error ** arm_A15_1: GEL Output: Byte Lane 1: arm_A15_1: GEL Output: DX1GSR2[6]: WEERR has ** No Error ** arm_A15_1: GEL Output: DX1GSR2[4]: REERR has ** No Error ** arm_A15_1: GEL Output: DX1GSR2[2]: WDERR has ** No Error ** arm_A15_1: GEL Output: DX1GSR2[0]: RDERR has ** No Error ** arm_A15_1: GEL Output: DX1GSR0[25]: QSGERR on Rank1 has ** No Error ** arm_A15_1: GEL Output: DX1GSR0[24]: QSGERR on Rank0 has ** No Error ** arm_A15_1: GEL Output: DX1GSR0[6]: WLERR has ** No Error ** arm_A15_1: GEL Output: Byte Lane 2: arm_A15_1: GEL Output: DX2GSR2[6]: WEERR has ** No Error ** arm_A15_1: GEL Output: DX2GSR2[4]: REERR has ** No Error ** arm_A15_1: GEL Output: DX2GSR2[2]: WDERR has ** No Error ** arm_A15_1: GEL Output: DX2GSR2[0]: RDERR has ** No Error ** arm_A15_1: GEL Output: DX2GSR0[25]: QSGERR on Rank1 has ** No Error ** arm_A15_1: GEL Output: DX2GSR0[24]: QSGERR on Rank0 has ** No Error ** arm_A15_1: GEL Output: DX2GSR0[6]: WLERR has ** No Error ** arm_A15_1: GEL Output: Byte Lane 3: arm_A15_1: GEL Output: DX3GSR2[6]: WEERR has ** No Error ** arm_A15_1: GEL Output: DX3GSR2[4]: REERR has ** No Error ** arm_A15_1: GEL Output: DX3GSR2[2]: WDERR has ** No Error ** arm_A15_1: GEL Output: DX3GSR2[0]: RDERR has ** No Error ** arm_A15_1: GEL Output: DX3GSR0[25]: QSGERR on Rank1 has ** No Error ** arm_A15_1: GEL Output: DX3GSR0[24]: QSGERR on Rank0 has ** No Error ** arm_A15_1: GEL Output: DX3GSR0[6]: WLERR has ** No Error ** arm_A15_1: GEL Output: Byte Lane 4: arm_A15_1: GEL Output: DX4GSR2[6]: WEERR has ** No Error ** arm_A15_1: GEL Output: DX4GSR2[4]: REERR has ** No Error ** arm_A15_1: GEL Output: DX4GSR2[2]: WDERR has ** No Error ** arm_A15_1: GEL Output: DX4GSR2[0]: RDERR has ** No Error ** arm_A15_1: GEL Output: DX4GSR0[25]: QSGERR on Rank1 has ** No Error ** arm_A15_1: GEL Output: DX4GSR0[24]: QSGERR on Rank0 has ** No Error ** arm_A15_1: GEL Output: DX4GSR0[6]: WLERR has ** No Error ** arm_A15_1: GEL Output: Byte Lane 5: arm_A15_1: GEL Output: DX5GSR2[6]: WEERR has ** No Error ** arm_A15_1: GEL Output: DX5GSR2[4]: REERR has ** No Error ** arm_A15_1: GEL Output: DX5GSR2[2]: WDERR has ** No Error ** arm_A15_1: GEL Output: DX5GSR2[0]: RDERR has ** No Error ** arm_A15_1: GEL Output: DX5GSR0[25]: QSGERR on Rank1 has ** No Error ** arm_A15_1: GEL Output: DX5GSR0[24]: QSGERR on Rank0 has ** No Error ** arm_A15_1: GEL Output: DX5GSR0[6]: WLERR has ** No Error ** arm_A15_1: GEL Output: Byte Lane 6: arm_A15_1: GEL Output: DX6GSR2[6]: WEERR has ** No Error ** arm_A15_1: GEL Output: DX6GSR2[4]: REERR has ** No Error ** arm_A15_1: GEL Output: DX6GSR2[2]: WDERR has ** No Error ** arm_A15_1: GEL Output: DX6GSR2[0]: RDERR has ** No Error ** arm_A15_1: GEL Output: DX6GSR0[25]: QSGERR on Rank1 has ** No Error ** arm_A15_1: GEL Output: DX6GSR0[24]: QSGERR on Rank0 has ** No Error ** arm_A15_1: GEL Output: DX6GSR0[6]: WLERR has ** No Error ** arm_A15_1: GEL Output: Byte Lane 7: arm_A15_1: GEL Output: DX7GSR2[6]: WEERR has ** No Error ** arm_A15_1: GEL Output: DX7GSR2[4]: REERR has ** No Error ** arm_A15_1: GEL Output: DX7GSR2[2]: WDERR has ** No Error ** arm_A15_1: GEL Output: DX7GSR2[0]: RDERR has ** No Error ** arm_A15_1: GEL Output: DX7GSR0[25]: QSGERR on Rank1 has ** No Error ** arm_A15_1: GEL Output: DX7GSR0[24]: QSGERR on Rank0 has ** No Error ** arm_A15_1: GEL Output: DX7GSR0[6]: WLERR has ** No Error ** arm_A15_1: GEL Output: Byte Lane 8: arm_A15_1: GEL Output: DX8GSR2[6]: WEERR has ** No Error ** arm_A15_1: GEL Output: DX8GSR2[4]: REERR has ** No Error ** arm_A15_1: GEL Output: DX8GSR2[2]: WDERR has ** No Error ** arm_A15_1: GEL Output: DX8GSR2[0]: RDERR has ** No Error ** arm_A15_1: GEL Output: DX8GSR0[25]: QSGERR on Rank1 has ** No Error ** arm_A15_1: GEL Output: DX8GSR0[24]: QSGERR on Rank0 has ** No Error ** arm_A15_1: GEL Output: DX8GSR0[6]: WLERR has ** No Error ** arm_A15_1: GEL Output: **************************************************************************************************************** arm_A15_1: GEL Output: **************************************************************************************************************** arm_A15_1: GEL Output: ***************** DDR3A Leveling Values ********************* arm_A15_1: GEL Output: DDR Clock Period as measured by Leveling Registers: arm_A15_1: GEL Output: DX0GSR0: 0x00379BA0 arm_A15_1: GEL Output: [14:7] (Write Leveling Period): 7 arm_A15_1: GEL Output: [23:16] (Read DQS Gating Period): 55 arm_A15_1: GEL Output: DX1GSR0: 0x00379BA0 arm_A15_1: GEL Output: [14:7] (Write Leveling Period): 7 arm_A15_1: GEL Output: [23:16] (Read DQS Gating Period): 55 arm_A15_1: GEL Output: DX2GSR0: 0x00379BA0 arm_A15_1: GEL Output: [14:7] (Write Leveling Period): 7 arm_A15_1: GEL Output: [23:16] (Read DQS Gating Period): 55 arm_A15_1: GEL Output: DX3GSR0: 0x00379BA0 arm_A15_1: GEL Output: [14:7] (Write Leveling Period): 7 arm_A15_1: GEL Output: [23:16] (Read DQS Gating Period): 55 arm_A15_1: GEL Output: DX4GSR0: 0x00379BA0 arm_A15_1: GEL Output: [14:7] (Write Leveling Period): 7 arm_A15_1: GEL Output: [23:16] (Read DQS Gating Period): 55 arm_A15_1: GEL Output: DX5GSR0: 0x00379BA0 arm_A15_1: GEL Output: [14:7] (Write Leveling Period): 7 arm_A15_1: GEL Output: [23:16] (Read DQS Gating Period): 55 arm_A15_1: GEL Output: DX6GSR0: 0x00379BA0 arm_A15_1: GEL Output: [14:7] (Write Leveling Period): 7 arm_A15_1: GEL Output: [23:16] (Read DQS Gating Period): 55 arm_A15_1: GEL Output: DX7GSR0: 0x00379BA0 arm_A15_1: GEL Output: [14:7] (Write Leveling Period): 7 arm_A15_1: GEL Output: [23:16] (Read DQS Gating Period): 55 arm_A15_1: GEL Output: DX8GSR0(ECC): 0x00379BA0 arm_A15_1: GEL Output: [14:7] (Write Leveling Period): 7 arm_A15_1: GEL Output: [23:16] (Read DQS Gating Period): 55 arm_A15_1: GEL Output: ******************************************************** arm_A15_1: GEL Output: Delay Values from Write Leveling Registers: arm_A15_1: GEL Output: DX0GTR: 0x00005003 arm_A15_1: GEL Output: [13:12] (Rank 0 WL Cycle Latency): 1 arm_A15_1: GEL Output: [15:14] (Rank 1 WL Cycle Latency): 1 arm_A15_1: GEL Output: DX0LCDLR0: 0x00000016 arm_A15_1: GEL Output: [7:0] (Rank 0 WL Delay): 22 arm_A15_1: GEL Output: [15:8] (Rank 1 WL Delay): 0 arm_A15_1: GEL Output: DX1GTR: 0x00005003 arm_A15_1: GEL Output: [13:12] (Rank 0 WL Cycle Latency): 1 arm_A15_1: GEL Output: [15:14] (Rank 1 WL Cycle Latency): 1 arm_A15_1: GEL Output: DX1LCDLR0: 0x00000017 arm_A15_1: GEL Output: [7:0] (Rank 0 WL Delay): 23 arm_A15_1: GEL Output: [15:8] (Rank 1 WL Delay): 0 arm_A15_1: GEL Output: DX2GTR: 0x00005002 arm_A15_1: GEL Output: [13:12] (Rank 0 WL Cycle Latency): 1 arm_A15_1: GEL Output: [15:14] (Rank 1 WL Cycle Latency): 1 arm_A15_1: GEL Output: DX2LCDLR0: 0x00000024 arm_A15_1: GEL Output: [7:0] (Rank 0 WL Delay): 36 arm_A15_1: GEL Output: [15:8] (Rank 1 WL Delay): 0 arm_A15_1: GEL Output: DX3GTR: 0x00005002 arm_A15_1: GEL Output: [13:12] (Rank 0 WL Cycle Latency): 1 arm_A15_1: GEL Output: [15:14] (Rank 1 WL Cycle Latency): 1 arm_A15_1: GEL Output: DX3LCDLR0: 0x00000028 arm_A15_1: GEL Output: [7:0] (Rank 0 WL Delay): 40 arm_A15_1: GEL Output: [15:8] (Rank 1 WL Delay): 0 arm_A15_1: GEL Output: DX4GTR: 0x00005003 arm_A15_1: GEL Output: [13:12] (Rank 0 WL Cycle Latency): 1 arm_A15_1: GEL Output: [15:14] (Rank 1 WL Cycle Latency): 1 arm_A15_1: GEL Output: DX4LCDLR0: 0x00000037 arm_A15_1: GEL Output: [7:0] (Rank 0 WL Delay): 55 arm_A15_1: GEL Output: [15:8] (Rank 1 WL Delay): 0 arm_A15_1: GEL Output: DX5GTR: 0x00005002 arm_A15_1: GEL Output: [13:12] (Rank 0 WL Cycle Latency): 1 arm_A15_1: GEL Output: [15:14] (Rank 1 WL Cycle Latency): 1 arm_A15_1: GEL Output: DX5LCDLR0: 0x00000042 arm_A15_1: GEL Output: [7:0] (Rank 0 WL Delay): 66 arm_A15_1: GEL Output: [15:8] (Rank 1 WL Delay): 0 arm_A15_1: GEL Output: DX6GTR: 0x00005003 arm_A15_1: GEL Output: [13:12] (Rank 0 WL Cycle Latency): 1 arm_A15_1: GEL Output: [15:14] (Rank 1 WL Cycle Latency): 1 arm_A15_1: GEL Output: DX6LCDLR0: 0x00000047 arm_A15_1: GEL Output: [7:0] (Rank 0 WL Delay): 71 arm_A15_1: GEL Output: [15:8] (Rank 1 WL Delay): 0 arm_A15_1: GEL Output: DX7GTR: 0x00005003 arm_A15_1: GEL Output: [13:12] (Rank 0 WL Cycle Latency): 1 arm_A15_1: GEL Output: [15:14] (Rank 1 WL Cycle Latency): 1 arm_A15_1: GEL Output: DX7LCDLR0: 0x0000004A arm_A15_1: GEL Output: [7:0] (Rank 0 WL Delay): 74 arm_A15_1: GEL Output: [15:8] (Rank 1 WL Delay): 0 arm_A15_1: GEL Output: DX8GTR: 0x00005002 arm_A15_1: GEL Output: [13:12] (Rank 0 WL Cycle Latency): 1 arm_A15_1: GEL Output: [15:14] (Rank 1 WL Cycle Latency): 1 arm_A15_1: GEL Output: DX8LCDLR0: 0x00000026 arm_A15_1: GEL Output: [7:0] (Rank 0 WL Delay): 38 arm_A15_1: GEL Output: [15:8] (Rank 1 WL Delay): 0 arm_A15_1: GEL Output: ******************************************************** arm_A15_1: GEL Output: Equivalent 90 degree phase shift in delay units, derived from measured period: arm_A15_1: GEL Output: DX0LCDLR1: 0x001C1C1F arm_A15_1: GEL Output: [7:0] (Write Delay Shift): 31 arm_A15_1: GEL Output: [15:8] (Read DQS Delay): 28 arm_A15_1: GEL Output: [23:16] (Read DQSN Delay): 28 arm_A15_1: GEL Output: DX1LCDLR1: 0x001B1B1F arm_A15_1: GEL Output: [7:0] (Write Delay Shift): 31 arm_A15_1: GEL Output: [15:8] (Read DQS Delay): 27 arm_A15_1: GEL Output: [23:16] (Read DQSN Delay): 27 arm_A15_1: GEL Output: DX2LCDLR1: 0x001D1D1F arm_A15_1: GEL Output: [7:0] (Write Delay Shift): 31 arm_A15_1: GEL Output: [15:8] (Read DQS Delay): 29 arm_A15_1: GEL Output: [23:16] (Read DQSN Delay): 29 arm_A15_1: GEL Output: DX3LCDLR1: 0x00191920 arm_A15_1: GEL Output: [7:0] (Write Delay Shift): 32 arm_A15_1: GEL Output: [15:8] (Read DQS Delay): 25 arm_A15_1: GEL Output: [23:16] (Read DQSN Delay): 25 arm_A15_1: GEL Output: DX4LCDLR1: 0x001B1B1E arm_A15_1: GEL Output: [7:0] (Write Delay Shift): 30 arm_A15_1: GEL Output: [15:8] (Read DQS Delay): 27 arm_A15_1: GEL Output: [23:16] (Read DQSN Delay): 27 arm_A15_1: GEL Output: DX5LCDLR1: 0x001B1B20 arm_A15_1: GEL Output: [7:0] (Write Delay Shift): 32 arm_A15_1: GEL Output: [15:8] (Read DQS Delay): 27 arm_A15_1: GEL Output: [23:16] (Read DQSN Delay): 27 arm_A15_1: GEL Output: DX6LCDLR1: 0x001C1C1D arm_A15_1: GEL Output: [7:0] (Write Delay Shift): 29 arm_A15_1: GEL Output: [15:8] (Read DQS Delay): 28 arm_A15_1: GEL Output: [23:16] (Read DQSN Delay): 28 arm_A15_1: GEL Output: DX7LCDLR1: 0x00191821 arm_A15_1: GEL Output: [7:0] (Write Delay Shift): 33 arm_A15_1: GEL Output: [15:8] (Read DQS Delay): 24 arm_A15_1: GEL Output: [23:16] (Read DQSN Delay): 25 arm_A15_1: GEL Output: DX8LCDLR1: 0x00191920 arm_A15_1: GEL Output: [7:0] (Write Delay Shift): 32 arm_A15_1: GEL Output: [15:8] (Read DQS Delay): 25 arm_A15_1: GEL Output: [23:16] (Read DQSN Delay): 25 arm_A15_1: GEL Output: ******************************************************** arm_A15_1: GEL Output: Delay Values from Read DQS Gating Leveling Registers: arm_A15_1: GEL Output: DX0GTR: 0x00005003 arm_A15_1: GEL Output: [2:0] (Rank 0 DQS Gating Latency): 3 arm_A15_1: GEL Output: [5:3] (Rank 1 DQS Gating Latency): 0 arm_A15_1: GEL Output: DX0LCDLR2: 0x00000015 arm_A15_1: GEL Output: [7:0] (Rank 0 RL Delay): 21 arm_A15_1: GEL Output: [15:8] (Rank 1 RL Delay): 0 arm_A15_1: GEL Output: DX1GTR: 0x00005003 arm_A15_1: GEL Output: [2:0] (Rank 0 DQS Gating Latency): 3 arm_A15_1: GEL Output: [5:3] (Rank 1 DQS Gating Latency): 0 arm_A15_1: GEL Output: DX1LCDLR2: 0x0000000F arm_A15_1: GEL Output: [7:0] (Rank 0 RL Delay): 15 arm_A15_1: GEL Output: [15:8] (Rank 1 RL Delay): 0 arm_A15_1: GEL Output: DX2GTR: 0x00005002 arm_A15_1: GEL Output: [2:0] (Rank 0 DQS Gating Latency): 2 arm_A15_1: GEL Output: [5:3] (Rank 1 DQS Gating Latency): 0 arm_A15_1: GEL Output: DX2LCDLR2: 0x0000004B arm_A15_1: GEL Output: [7:0] (Rank 0 RL Delay): 75 arm_A15_1: GEL Output: [15:8] (Rank 1 RL Delay): 0 arm_A15_1: GEL Output: DX3GTR: 0x00005002 arm_A15_1: GEL Output: [2:0] (Rank 0 DQS Gating Latency): 2 arm_A15_1: GEL Output: [5:3] (Rank 1 DQS Gating Latency): 0 arm_A15_1: GEL Output: DX3LCDLR2: 0x00000047 arm_A15_1: GEL Output: [7:0] (Rank 0 RL Delay): 71 arm_A15_1: GEL Output: [15:8] (Rank 1 RL Delay): 0 arm_A15_1: GEL Output: DX4GTR: 0x00005003 arm_A15_1: GEL Output: [2:0] (Rank 0 DQS Gating Latency): 3 arm_A15_1: GEL Output: [5:3] (Rank 1 DQS Gating Latency): 0 arm_A15_1: GEL Output: DX4LCDLR2: 0x00000002 arm_A15_1: GEL Output: [7:0] (Rank 0 RL Delay): 2 arm_A15_1: GEL Output: [15:8] (Rank 1 RL Delay): 0 arm_A15_1: GEL Output: DX5GTR: 0x00005002 arm_A15_1: GEL Output: [2:0] (Rank 0 DQS Gating Latency): 2 arm_A15_1: GEL Output: [5:3] (Rank 1 DQS Gating Latency): 0 arm_A15_1: GEL Output: DX5LCDLR2: 0x0000005E arm_A15_1: GEL Output: [7:0] (Rank 0 RL Delay): 94 arm_A15_1: GEL Output: [15:8] (Rank 1 RL Delay): 0 arm_A15_1: GEL Output: DX6GTR: 0x00005003 arm_A15_1: GEL Output: [2:0] (Rank 0 DQS Gating Latency): 3 arm_A15_1: GEL Output: [5:3] (Rank 1 DQS Gating Latency): 0 arm_A15_1: GEL Output: DX6LCDLR2: 0x00000045 arm_A15_1: GEL Output: [7:0] (Rank 0 RL Delay): 69 arm_A15_1: GEL Output: [15:8] (Rank 1 RL Delay): 0 arm_A15_1: GEL Output: DX7GTR: 0x00005003 arm_A15_1: GEL Output: [2:0] (Rank 0 DQS Gating Latency): 3 arm_A15_1: GEL Output: [5:3] (Rank 1 DQS Gating Latency): 0 arm_A15_1: GEL Output: DX7LCDLR2: 0x00000004 arm_A15_1: GEL Output: [7:0] (Rank 0 RL Delay): 4 arm_A15_1: GEL Output: [15:8] (Rank 1 RL Delay): 0 arm_A15_1: GEL Output: DX8GTR: 0x00005002 arm_A15_1: GEL Output: [2:0] (Rank 0 DQS Gating Latency): 2 arm_A15_1: GEL Output: [5:3] (Rank 1 DQS Gating Latency): 0 arm_A15_1: GEL Output: DX8LCDLR2: 0x0000005F arm_A15_1: GEL Output: [7:0] (Rank 0 RL Delay): 95 arm_A15_1: GEL Output: [15:8] (Rank 1 RL Delay): 0 arm_A15_1: GEL Output: ****************************************************************************************************************