SBL Revision: 01.00.10.00 (May 27 2021 - 13:53:44) TIFS ver: 20.8.5--v2020.08b (Terrific Lla SCISERVER Board Configuration header population... PASSED Sciclient_setBoardConfigHeader... PASSED Initlialzing PLLs ...done. InitlialzingClocks ...done. Initlialzing DDR ...done. Initializing GTC ...Begin parsing user application Calling Sciclient_procBootRequestProcessor, ProcId 0x20... Calling Sciclient_procBootRequestProcessor, ProcId 0x21... Calling Sciclient_procBootRequestProcessor, ProcId 0x1... Calling Sciclient_procBootRequestProcessor, ProcId 0x2... Calling Sciclient_procBootRequestProcessor, ProcId 0x6... Calling Sciclient_procBootRequestProcessor, ProcId 0x7... Searching for X509 certificate ...not found Switching core id 4, proc_id 0x1 to split mode... Calling Sciclient_procBootGetProcessorState, ProcId 0x1... Sciclient_procBootSetProcessorCfg, ProcId 0x1, enabling split mode... Calling Sciclient_procBootGetProcessorState, ProcId 0x1... Enabling MCU TCMs after reset for core 4 Disabling HW-based memory init of MCU TCMs for core 4 Sciclient_procBootSetProcessorCfg enabling TCMs... Copying 0x40 bytes to 0x41010000 Copying 0x2c88 bytes to 0x41010100 Copying 0x500 bytes to 0x41015980 Copying 0x28 bytes to 0x41015e80 Copying 0x10 bytes to 0x41015ea8 Copying 0x13f40 bytes to 0x41c9c320 Copying 0x6e50 bytes to 0x41cb0260 Copying 0x1500 bytes to 0x41cbac00 Copying 0xb30 bytes to 0x41cbc100 Setting entry point for core 4 @0x41010000 Sciclient_pmSetModuleState On, DevId 0x4... Copying 0x7a0 bytes to 0x70040000 Copying 0xc398 bytes to 0x70092000 Copying 0x18c bytes to 0x7009e398 Copying 0xce0 bytes to 0x7009e528 Copying 0x498 bytes to 0x7009f210 Copying 0x6468 bytes to 0x7009f6a8 Setting entry point for core 0 @0x70092558 Sciclient_procBootSetProcessorCfg, ProcId 0x20, EntryPoint 0x70092558... Sciclient_pmQueryModuleClkFreq, DevId 0xca @ 1200000000Hz... PLL8_SS_CTRL Register Value = 0x80000001 Sciclient_pmSetModuleClkFreq, DevId 0xca @ 1200000000Hz... Sciclient_pmGetModuleClkFreq, DevId 0xca @ 1200000000Hz... CTRLMMR_WKUP_MAIN_PLL8_CLKSEL Register Value = 0x800000 BYPASS_SW_OVRD Field Value = 0x0 BYP_WARM_RST Field Value = 0x1 CLK_SEL Field Value = 0x0 PLL8_FREQ_CTRL0 Register Value = 0x7d FB_DIV_INT Field Value = 0x7d PLL8_FREQ_CTRL1 Register Value = 0x0 FB_DIV_FRAC Field Value = 0x0 PLL8_DIV_CTRL Register Value = 0x1020001 POST_DIV2 Field Value = 0x1 POST_DIV1 Field Value = 0x2 REF_DIV Field Value = 0x1 PLL8_SS_CTRL Register Value = 0x80000001 BYPASS_EN Field Value = 0x1 WV_TBLE_MAXADDR Field Value = 0x0 RESET Field Value = 0x0 DOWNSPREAD_EN Field Value = 0x0 WAVE_SEL Field Value = 0x1 PLL8_SS_SPREAD Value = 0x10001 MOD_DIV Field Value = 0x1 SPREAD Field Value = 0x1 PLL8_HSDIV_CTRL0 Register Value = 0x8001 RESET Field Value = 0x0 CLKOUT_EN Field Value = 0x1 SYNC_DIS Field Value = 0x0 HSDIV Field Value = 0x1 Sciclient_pmSetModuleState Off, DevId 0xca... Sciclient_pmSetModuleState On, DevId 0xca... Sciclient_procBootReleaseProcessor, ProcId 0x20... Sciclient_procBootReleaseProcessor, ProcId 0x21... Sciclient_procBootReleaseProcessor, ProcId 0x1... Sciclient_procBootReleaseProcessor, ProcId 0x2... Sciclient_procBootReleaseProcessor, ProcId 0x6... Sciclient_procBootReleaseProcessor, ProcId 0x7... Calling Sciclient_procBootRequestProcessor, ProcId 0x1... Sciclient_procBootSetProcessorCfg, ProcId 0x1, EntryPoint 0x41010000... Sciclient_pmQueryModuleClkFreq, DevId 0xfa @ 1000000000Hz... Sciclient_pmSetModuleClkFreq, DevId 0xfa @ 1000000000Hz... Sciclient_pmGetModuleClkFreq, DevId 0xfa @ 1000000000Hz... Copying first 128 bytes from app to MCU ATCM @ 0x0 for core 4 Calling Sciclient_procBootRequestProcessor, ProcId 0x2... Skipping Sciclient_procBootSetProcessorCfg for ProcId 0x2, EntryPoint 0xfffffffe... Calling Sciclient_procBootRequestProcessor, ProcId 0x1... Sciserver Built On: Nov 5 2020 22:47:06 Starting Sciserver..... PASSED