void PINMUX_Config(void) { //Address Lines /* GPMC_A1 */ HWREG(SOC_CONTROL_REGS + conf_lcd_data1_offset) = ( 1 << CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_PUDEN_SHIFT) | ( 0 << CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_RXACTIVE_SHIFT); /* GPMC_A2 */ HWREG(SOC_CONTROL_REGS + conf_lcd_data2_offset) = ( 1 << CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_PUDEN_SHIFT)| ( 0 << CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_RXACTIVE_SHIFT) ; /* GPMC_A3 */ HWREG(SOC_CONTROL_REGS + conf_lcd_data3_offset) = ( 1 << CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_PUDEN_SHIFT)| ( 0 << CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_RXACTIVE_SHIFT) ; /* GPMC_A4 */ HWREG(SOC_CONTROL_REGS + conf_lcd_data4_offset) = ( 1 << CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_PUDEN_SHIFT)| ( 0 << CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_RXACTIVE_SHIFT) ; /* GPMC_A5 */ HWREG(SOC_CONTROL_REGS + conf_lcd_data5_offset) = ( 1 << CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_PUDEN_SHIFT)| ( 0 << CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_RXACTIVE_SHIFT) ; /* GPMC_A6 */ HWREG(SOC_CONTROL_REGS + conf_lcd_data6_offset) = ( 1 << CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_PUDEN_SHIFT)| ( 0 << CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_RXACTIVE_SHIFT) ; /* GPMC_AD7 */ HWREG(SOC_CONTROL_REGS + conf_lcd_data7_offset) = ( 1 << CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_PUDEN_SHIFT)| ( 0 << CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_RXACTIVE_SHIFT) ; /* GPMC_A8 */ HWREG(SOC_CONTROL_REGS + vsync_offset) = ( 1 << CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_PUDEN_SHIFT)| ( 0 << CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_RXACTIVE_SHIFT) ; /* GPMC_A9 */ HWREG(SOC_CONTROL_REGS + hsync_offset) = ( 1 << CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_PUDEN_SHIFT)| ( 0 << CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_RXACTIVE_SHIFT) ; /* GPMC_A10 */ HWREG(SOC_CONTROL_REGS + pclk_offset) = ( 1 << CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_PUDEN_SHIFT)| ( 0 << CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_RXACTIVE_SHIFT) ; /* GPMC_A11 */ HWREG(SOC_CONTROL_REGS + ac_bias_en_offset) = ( 1 << CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_PUDEN_SHIFT)| ( 0 << CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_RXACTIVE_SHIFT) ; /* GPMC_A12 */ HWREG(SOC_CONTROL_REGS + lcd_data8_offset) = ( 1 << CONTROL_CONF_GPMC_A12_CONF_GPMC_A12_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_A12_CONF_GPMC_A12_PUDEN_SHIFT)| ( 0 << CONTROL_CONF_GPMC_A12_CONF_GPMC_A12_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_A12_CONF_GPMC_A12_RXACTIVE_SHIFT) ; /* GPMC_A13 */ HWREG(SOC_CONTROL_REGS + lcd_data9_offset) = ( 1 << CONTROL_CONF_GPMC_A13_CONF_GPMC_A13_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_A13_CONF_GPMC_A13_PUDEN_SHIFT)| ( 0 << CONTROL_CONF_GPMC_A13_CONF_GPMC_A13_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_A13_CONF_GPMC_A13_RXACTIVE_SHIFT) ; /* GPMC_A14 */ HWREG(SOC_CONTROL_REGS + lcd_data10_offset) = ( 1 << CONTROL_CONF_GPMC_A14_CONF_GPMC_A14_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_A14_CONF_GPMC_A14_PUDEN_SHIFT)| ( 0 << CONTROL_CONF_GPMC_A14_CONF_GPMC_A14_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_A14_CONF_GPMC_A14_RXACTIVE_SHIFT) ; /* GPMC_A15 */ HWREG(SOC_CONTROL_REGS + lcd_data11_offset) = ( 1 << CONTROL_CONF_GPMC_A15_CONF_GPMC_A15_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_A15_CONF_GPMC_A15_PUDEN_SHIFT)| ( 0 << CONTROL_CONF_GPMC_A15_CONF_GPMC_A15_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_A15_CONF_GPMC_A15_RXACTIVE_SHIFT) ; /* GPMC_A16 */ HWREG(SOC_CONTROL_REGS + conf_gpmc_a0_offset) = ( 4 << CONTROL_CONF_GPMC_A16_CONF_GPMC_A16_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_A16_CONF_GPMC_A16_PUDEN_SHIFT)| ( 0 << CONTROL_CONF_GPMC_A16_CONF_GPMC_A16_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_A16_CONF_GPMC_A16_RXACTIVE_SHIFT); //Data Lines /* GPMC_AD0 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(0)) = ( 0 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUDEN_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE_SHIFT); /* GPMC_AD1 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(1)) = ( 0 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUDEN_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_RXACTIVE_SHIFT); /* GPMC_AD2 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(2)) = ( 0 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUDEN_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_RXACTIVE_SHIFT); /* GPMC_AD3 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(3)) = ( 0 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUDEN_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_RXACTIVE_SHIFT); /* GPMC_AD4 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(4)) = ( 0 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUDEN_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_RXACTIVE_SHIFT); /* GPMC_AD5 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(5)) = ( 0 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUDEN_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_RXACTIVE_SHIFT); /* GPMC_AD6 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(6)) = ( 0 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUDEN_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_RXACTIVE_SHIFT); /* GPMC_AD7 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(7)) = ( 0 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUDEN_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_RXACTIVE_SHIFT); /* GPMC_AD8 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(8)) = ( 0 << CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_PUDEN_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_RXACTIVE_SHIFT); /* GPMC_AD9*/ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(9)) = ( 0 << CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_PUDEN_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_RXACTIVE_SHIFT); /* GPMC_AD10*/ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(10)) = ( 0 << CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_PUDEN_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_RXACTIVE_SHIFT); /* GPMC_AD11*/ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(11)) = ( 0 << CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_PUDEN_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_RXACTIVE_SHIFT); /* GPMC_AD12*/ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(12)) = ( 0 << CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_PUDEN_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_RXACTIVE_SHIFT); /* GPMC_AD13*/ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(13)) = ( 0 << CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_PUDEN_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_RXACTIVE_SHIFT); /* GPMC_AD14*/ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(14)) = ( 0 << CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_PUDEN_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_RXACTIVE_SHIFT); /* GPMC_AD15 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(15)) = ( 0 << CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_PUDEN_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_PUTYPESEL_SHIFT) | ( 1 << CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_RXACTIVE_SHIFT); //PUTYPESEL bit to be verified /* GPMC_WAIT0 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WAIT0) = ( 0 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUDEN_SHIFT) | ( 0 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUTYPESEL_SHIFT)| ( 0 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_RXACTIVE_SHIFT); /* GPMC_CS3 */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_CSN(3)) = ( 0 << CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_PUDEN_SHIFT)| ( 0 << CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_PUTYPESEL_SHIFT)| ( 0 << CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_RXACTIVE_SHIFT); /* GPMC_BE0N_CLE */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_BE0N_CLE) = ( 0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_MMODE_SHIFT ) | ( 0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUDEN_SHIFT ) | ( 0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUTYPESEL_SHIFT) | ( 0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_RXACTIVE_SHIFT); /* GPMC_OEN_REN */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_OEN_REN) = ( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUDEN_SHIFT) | ( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUTYPESEL_SHIFT) | ( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_RXACTIVE_SHIFT); /* GPMC_WEN */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WEN) = ( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUDEN_SHIFT) | ( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUTYPESEL_SHIFT) | ( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RXACTIVE_SHIFT); /* GPMC_BE1N_CLE */ HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_BE1N) = ( 0 << CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_MMODE_SHIFT ) | ( 0 << CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_PUDEN_SHIFT ) | ( 0 << CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_PUTYPESEL_SHIFT) | ( 0 << CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_RXACTIVE_SHIFT); /* DPRAM INTR GPIO0_8*/ HWREG(SOC_CONTROL_REGS + lcd_data12_offset) = ( 7 << CONTROL_CONF_GPMC_A16_CONF_GPMC_A16_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_A16_CONF_GPMC_A16_PUDEN_SHIFT)| ( 0 << CONTROL_CONF_GPMC_A16_CONF_GPMC_A16_PUTYPESEL_SHIFT) | ( 0 << CONTROL_CONF_GPMC_A16_CONF_GPMC_A16_RXACTIVE_SHIFT); /* DPRAM SEM GPIO0_9 */ HWREG(SOC_CONTROL_REGS + lcd_data13_offset) = ( 7 << CONTROL_CONF_GPMC_A16_CONF_GPMC_A16_MMODE_SHIFT) | ( 0 << CONTROL_CONF_GPMC_A16_CONF_GPMC_A16_PUDEN_SHIFT)| ( 0 << CONTROL_CONF_GPMC_A16_CONF_GPMC_A16_PUTYPESEL_SHIFT) | ( 0 << CONTROL_CONF_GPMC_A16_CONF_GPMC_A16_RXACTIVE_SHIFT); } void GPMC_DPRAM_Init(void) { int csNum = 3; unsigned int temp; //enable clock to GPMC module HWREG(SOC_PRCM_REGS + CM_PER_GPMC_CLKCTRL ) |= CM_PER_GPMC_CLKCTRL_MODULEMODE_ENABLE; //check to see if enabled while((HWREG(SOC_PRCM_REGS + CM_PER_GPMC_CLKCTRL) & CM_PER_GPMC_CLKCTRL_IDLEST) != (CM_PER_GPMC_CLKCTRL_IDLEST_FUNC << CM_PER_GPMC_CLKCTRL_IDLEST_SHIFT)); //reset the GPMC module HWREG(SOC_GPMC_0_REGS + GPMC_SYSCONFIG ) |= GPMC_SYSCONFIG_SOFTRESET; while((HWREG(SOC_GPMC_0_REGS + GPMC_SYSSTATUS) & GPMC_SYSSTATUS_RESETDONE) == GPMC_SYSSTATUS_RESETDONE_RSTONGOING); //Configure to no idle temp = HWREG(SOC_GPMC_0_REGS + GPMC_SYSCONFIG); temp &= ~GPMC_SYSCONFIG_IDLEMODE; temp |= GPMC_SYSCONFIG_IDLEMODE_NOIDLE << GPMC_SYSCONFIG_IDLEMODE_SHIFT; HWREG(SOC_GPMC_0_REGS + GPMC_SYSCONFIG) = temp; HWREG(SOC_GPMC_0_REGS + GPMC_IRQENABLE) = 0x0; HWREG(SOC_GPMC_0_REGS + GPMC_TIMEOUT_CONTROL) = 0x0; HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG) = 0x2; HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG1(csNum )) = 0x00001000; ; HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG2(csNum )) = 0x00070800; HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG3(csNum )) = 0x00020200; HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG4(csNum )) = 0x07000800; HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG5(csNum )) = 0x00070708; HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG6(csNum )) = 0x00000180; HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG7(csNum )) = 0x00000F49; //address space starts at 0x09000000 } void MMUConfigAndEnable(void) { /* ** Define DDR memory region of AM335x. DDR can be configured as Normal ** memory with R/W access in user/privileged modes. The cache attributes ** specified here are, ** Inner - Write through, No Write Allocate ** Outer - Write Back, Write Allocate */ REGION regionDdr = { MMU_PGTYPE_SECTION, START_ADDR_DDR, NUM_SECTIONS_DDR, MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_CACHE_WT_NOWA, MMU_CACHE_WB_WA), MMU_REGION_NON_SECURE, MMU_AP_PRV_RW_USR_RW, (unsigned int*)pageTable }; /* ** Define OCMC RAM region of AM335x. Same Attributes of DDR region given. */ REGION regionOcmc = { MMU_PGTYPE_SECTION, START_ADDR_OCMC, NUM_SECTIONS_OCMC, MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_CACHE_WT_NOWA, MMU_CACHE_WB_WA), MMU_REGION_NON_SECURE, MMU_AP_PRV_RW_USR_RW, (unsigned int*)pageTable }; /* ** Define Device Memory Region. The region between OCMC and DDR is ** configured as device memory, with R/W access in user/privileged modes. ** Also, the region is marked 'Execute Never'. */ REGION regionDev = { MMU_PGTYPE_SECTION, START_ADDR_DEV, NUM_SECTIONS_DEV, MMU_MEMTYPE_DEVICE_SHAREABLE, MMU_REGION_NON_SECURE, MMU_AP_PRV_RW_USR_RW | MMU_SECTION_EXEC_NEVER, (unsigned int*)pageTable }; /* Initialize the page table and MMU */ MMUInit((unsigned int*)pageTable); /* Map the defined regions */ MMUMemRegionMap(®ionDdr); MMUMemRegionMap(®ionOcmc); MMUMemRegionMap(®ionDev); /* Now Safe to enable MMU */ MMUEnable((unsigned int*)pageTable); } void main() { unsigned int error = 0; unsigned int i; unsigned int *pmem; MMUConfigAndEnable(); GPMC_DPRAM_Init(); PINMUX_Config(); while(1) { pmem = (unsigned int *) 0x09000000; // fill data for(i=0; i<0x2; i+=2) { *pmem++ = 0x1234; // After this instruction getting exception } // verify data pmem = (unsigned int *) 0x09000000; for(i=0; i<0x20; i+=1) { if(*pmem++ != 0x12) error++; else { error = error; } } } } /****************************************************************************** ** END OF FILE *******************************************************************************/ /**************** Memory Map Configuration On Target Connect ************************/ OnTargetConnect() { GEL_MapOff(); GEL_MapReset(); GEL_MapAddStr(0x00020000, 0, 0x0000C000, "R", 0); // Boot ROM GEL_MapAddStr(0x08000000, 0, 0x00100000, "R|W", 0); // 16MB GPMC External/NOR (on GP Daughtercard) GEL_MapAddStr(0x09000000, 0, 0x00080000, "R|W", 0); // GPMC DPRAM GEL_MapAddStr(0x40020000, 0, 0x0000C000, "R", 0); // Boot ROM (also at 0x20000) GEL_MapAddStr(0x402F0400, 0, 0x0000FC00, "R|W", 0); // SRAM Internal GEL_MapAddStr(0x40300000, 0, 0x00010000, "R|W", 0); // OCMC-RAM GEL_MapAddStr(0x44000000, 0, 0x00400000, "R|W", 0); // L3F CFG Regs GEL_MapAddStr(0x44800000, 0, 0x00400000, "R|W", 0); // L3S CFG Regs GEL_MapAddStr(0x44C00000, 0, 0x00400000, "R|W", 0); // L4_WKUP GEL_MapAddStr(0x46000000, 0, 0x00400000, "R|W", 0); // McASP0 Data GEL_MapAddStr(0x46400000, 0, 0x00400000, "R|W", 0); // McASP1 Data GEL_MapAddStr(0x47400000, 0, 0x00005000, "R|W", 0); // USB0/1 GEL_MapAddStr(0x47810000, 0, 0x00010000, "R|W", 0); // MMCHS2 GEL_MapAddStr(0x48000000, 0, 0x01000000, "R|W", 0); // L4 PER GEL_MapAddStr(0x49000000, 0, 0x00B00000, "R|W", 0); // EDMA GEL_MapAddStr(0x4A000000, 0, 0x01000000, "R|W", 0); // L4_FAST GEL_MapAddStr(0x4B160000, 0, 0x1000, "R|W", 0); // DebugSS_DRM GEL_MapAddStr(0x4C000000, 0, 0x01000000, "R|W", 0); // EMIF GEL_MapAddStr(0x50000000, 0, 0x01000000, "R|W", 0); // GPMC Regs GEL_MapAddStr(0x56000000, 0, 0x01000000, "R|W", 0); // SGX530 GEL_MapAddStr(0x80000000, 0, 0x20000000, "R|W", 0); // 512MB DDR2 external memory GEL_MapOn(); AM335xStartState(); AM335x_EVM_Initialization(); DDR_DataTransferCheck(); Disable_Watchdog(); } /*******************************************************************************************