---------------------------------------------------------------------------------Ti EVM Log: [Cortex_M4_IPU1_C0] MAC Port 0 Address: d4-f5-13-b4-62-90 MAC Port 1 Address: d4-f5-13-b4-62-91 GMACSW has been started successfully Registration of the GMACSW Successful Service Status: DHCPC : Enabled : : 000 Service Status: Telnet : Enabled : : 000 Service Status: HTTP : Enabled : : 000 Service Status: HTTP : Enabled : : 000 Service Status: DHCPC : Enabled : Running : 000 PHY: 2, NegMode 01E1, NWAYadvertise 01E1, NWAYREadvertise 43E1 Negotiated connection: FullDuplex 100 Mbs Link Status: 100Mb/s Full Duplex on PHY 2 Network Added: If-1:192.168.213.7 Service Status: DHCPC : Enabled : Running : 017 ---------------------------------------------------------------------------------Eric EVM: MII mode for dp83848q Phy [Cortex_M4_IPU1_C0] MAC Port 0 Address: d0-b5-c2-5b-42-ee MAC Port 1 Address: d0-b5-c2-5b-42-ef GMACSW has been started successfully Registration of the GMACSW Successful Service Status: DHCPC : Enabled : : 000 Service Status: Telnet : Enabled : : 000 Service Status: HTTP : Enabled : : 000 Service Status: HTTP : Enabled : : 000 Service Status: DHCPC : Enabled : Running : 000 ---------------------------------------------------------------------------------Eric EVM: CCS Log for running gel file Cortex_M4_IPU1_C0: GEL Output: --->>> TDA2xx Cortex M4 Startup Sequence In Progress... <<<--- Cortex_M4_IPU1_C0: GEL Output: --->>> TDA2xx Cortex M4 Startup Sequence DONE! <<<--- Cortex_M4_IPU1_C1: GEL Output: --->>> TDA2xx Cortex M4 Startup Sequence In Progress... <<<--- Cortex_M4_IPU1_C1: GEL Output: --->>> TDA2xx Cortex M4 Startup Sequence DONE! <<<--- C66xx_DSP1: GEL Output: --->>> TDA2xx C66x DSP Startup Sequence In Progress... <<<--- C66xx_DSP1: GEL Output: --->>> TDA2xx C66x DSP Startup Sequence DONE! <<<--- C66xx_DSP2: GEL Output: --->>> TDA2xx C66x DSP Startup Sequence In Progress... <<<--- C66xx_DSP2: GEL Output: --->>> TDA2xx C66x DSP Startup Sequence DONE! <<<--- CortexA15_0: GEL Output: --->>> TDA2xx Cortex A15 Startup Sequence In Progress... <<<--- CortexA15_0: GEL Output: --->>> TDA2xx Cortex A15 Startup Sequence DONE! <<<--- ARP32_EVE_1: GEL Output: --->>> Configuring EVE Memory Map <<<--- ARP32_EVE_1: GEL Output: --->>> EVE Memory Map Done! <<<--- ARP32_EVE_2: GEL Output: --->>> Configuring EVE Memory Map <<<--- ARP32_EVE_2: GEL Output: --->>> EVE Memory Map Done! <<<--- ARP32_EVE_3: GEL Output: --->>> Configuring EVE Memory Map <<<--- ARP32_EVE_3: GEL Output: --->>> EVE Memory Map Done! <<<--- ARP32_EVE_4: GEL Output: --->>> Configuring EVE Memory Map <<<--- ARP32_EVE_4: GEL Output: --->>> EVE Memory Map Done! <<<--- IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset. IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset. IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset. IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset. IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset. CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs <<<--- CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress... CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<---- CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> --- CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<---- CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do. CortexA15_0: GEL Output: --->>> TDA2xx Target Connect Sequence Begins ... <<<--- CortexA15_0: GEL Output: --->>> TDA2xx PG1.0 GP device <<<--- CortexA15_0: GEL Output: --->>> The core is in non-SECURE state. <<<--- CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<--- CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: Cortex A15 DPLL is already locked, now unlocking... CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 is DONE! CortexA15_0: GEL Output: IVA DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: IVA DPLL OPP 0 is DONE! CortexA15_0: GEL Output: PER DPLL OPP 0 clock config in progress... CortexA15_0: GEL Output: PER DPLL already locked, now unlocking CortexA15_0: GEL Output: PER DPLL OPP 0 is DONE! CortexA15_0: GEL Output: CORE DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: CORE DPLL OPP already locked, now unlocking.... CortexA15_0: GEL Output: CORE DPLL OPP 0 is DONE! CortexA15_0: GEL Output: ABE DPLL OPP 0 clock config in progress... CortexA15_0: GEL Output: ABE DPLL OPP 0 is DONE! CortexA15_0: GEL Output: GMAC DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: GMAC DPLL OPP 0 is DONE! CortexA15_0: GEL Output: GPU DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: GPU DPLL OPP 0 is DONE! CortexA15_0: GEL Output: DSP DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: DSP DPLL OPP 0 is DONE! CortexA15_0: GEL Output: EVE DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: EVE DPLL OPP 0 is DONE! CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 is DONE! CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<--- CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<--- CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<--- CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in progress... CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in DONE! CortexA15_0: GEL Output: Launch full leveling CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers CortexA15_0: GEL Output: as per HW leveling output CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from CortexA15_0: GEL Output: PHY_STATUSx registers CortexA15_0: GEL Output: Launch full leveling CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers CortexA15_0: GEL Output: as per HW leveling output CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from CortexA15_0: GEL Output: PHY_STATUSx registers CortexA15_0: GEL Output: One EMIF - 512MB total memory CortexA15_0: GEL Output: Same memory mapped at 0x80000000 and 0xA0000000 CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> TDA2xx Begin All Pad Configuration for PAB MII Usage <<<--- CortexA15_0: GEL Output: --->>> TDA2xx Begin GMAC_SW MDIO Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> TDA2xx End GMAC_SW MDIO Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> TDA2xx Begin GMAC_SW MII0 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> TDA2xx End GMAC_SW MII0 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> TDA2xx Begin GMAC_SW MII1 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> TDA2xx End GMAC_SW MII1 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> TDA2xx End All Pad Configuration for PAB MII Usage <<<--- CortexA15_0: GEL Output: --->>> TDA2xx Target Connect Sequence DONE !!!!! <<<--- Cortex_M4_IPU1_C0: Error connecting to the target: (Error -1266 @ 0x0) Device is held in reset. Take the device out of reset, and retry the operation. (Emulation package 6.0.407.3) CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> EVE1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ... CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 1: 0x00000000 --> 0x80000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 2: 0x80000000 --> 0x80000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 3: 0x40000000 --> 0x40000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 4: 0x48000000 --> 0x48000000 CortexA15_0: GEL Output: DEBUG: EVE0 MMU0 configured as per VisionSDK requirements!!!! CortexA15_0: GEL Output: --->>> EVE1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> EVE2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ... CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 1: 0x00000000 --> 0x81000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 2: 0x81000000 --> 0x81000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 3: 0x40000000 --> 0x40000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 4: 0x48000000 --> 0x48000000 CortexA15_0: GEL Output: DEBUG: EVE0 MMU0 configured as per VisionSDK requirements!!!! CortexA15_0: GEL Output: --->>> EVE2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> EVE3SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ... CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 1: 0x00000000 --> 0x82000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 2: 0x82000000 --> 0x82000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 3: 0x40000000 --> 0x40000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 4: 0x48000000 --> 0x48000000 CortexA15_0: GEL Output: DEBUG: EVE0 MMU0 configured as per VisionSDK requirements!!!! CortexA15_0: GEL Output: --->>> EVE3SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> EVE4SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ... CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 1: 0x00000000 --> 0x83000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 2: 0x83000000 --> 0x83000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 3: 0x40000000 --> 0x40000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 4: 0x48000000 --> 0x48000000 CortexA15_0: GEL Output: DEBUG: EVE0 MMU0 configured as per VisionSDK requirements!!!! CortexA15_0: GEL Output: --->>> EVE4SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<--- CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---