/*! * File generated by platform wizard. DO NOT MODIFY * */ metaonly module Platform inherits xdc.platform.IPlatform { config ti.platforms.generic.Platform.Instance CPU = ti.platforms.generic.Platform.create("CPU", { clockRate: 456.0, catalogName: "ti.catalog.c6000", deviceName: "OMAPL138", customMemoryMap: [ ["IROM", { name: "IROM", base: 0x11700000, len: 0x00100000, space: "code/data", access: "RX", } ], ["L3_CBA_RAM", { name: "L3_CBA_RAM", base: 0x80000000, len: 0x00020000, space: "code/data", access: "RWX", } ], ["DDR", { name: "DDR", base: 0xc4010000, len: 0x01000000, space: "code/data", access: "RWX", } ], ["entry_point", { name: "entry_point", base: 0xc4000000, len: 0x00000100, space: "code/data", access: "RWX", } ], ], l2Mode: "0k", l1PMode: "0k", l1DMode: "0k", }); instance : override config string codeMemory = "DDR"; override config string dataMemory = "DDR"; override config string stackMemory = "DDR"; config String l2Mode = "0k"; config String l1PMode = "0k"; config String l1DMode = "0k"; }