/*----------------------------------------------------------------------------*/ /* File: R5_LINKER.lds */ /* Description: */ /* linker file for MCU R5F core0 */ /*----------------------------------------------------------------------------*/ /* History: */ /*----------------------------------------------------------------------------*/ /* Linker Settings */ /* Standard linker options */ --retain="*(.STARTUP)" --retain="*(.rstvectors)" --retain="*(VECT)" --retain="*(SYS)" --retain="*(inttable)" --retain="*(.irqStack)" --retain="*(syscall)" --retain="*(.fiqStack)" --retain="*(.abortStack)" --retain="*(.undStack)" --retain="*(.svcStack)" --fill_value=0 --stack_size=0x2000 --heap_size=0x1000 --entry_point=_resetvectors /* Default C RTS boot.asm */ -stack 0x8000 /* SOFTWARE STACK SIZE */ -heap 0x5000 --define FILL_PATTERN=0xFEAA55EF --define FILL_LENGTH=0x100 __IRQ_STACK_SIZE = 0x2000; __FIQ_STACK_SIZE = 0x2000; __ABORT_STACK_SIZE = 0x1000; __UND_STACK_SIZE = 0x1000; __SVC_STACK_SIZE = 0x1000; /* HEAP AREA SIZE */ /*Classic autosar stack memory details*/ #define CA_CODE_START 0x90000000 //#define CA_CODE_LEN 0x40000‬ #define CA_CONST_DATA_START 0x9003E000 #define CA_CONST_DATA_LEN 0x0000F000 //#define CA_RAM_NOINIT_START 0x9004D000‬ #define CA_RAM_NOINIT_LEN 0x00014000 #define CA_RAM_CLR_START 0x90061000 #define CA_RAM_CLR_LEN 0x00010400 #define CA_RAM_INIT_START 0x90071400 #define CA_RAM_INIT_LEN 0x00005000 #define CA_RAM_DATA_START 0x90076400 #define CA_RAM_DATA_LEN 0x00014000 #define CA_EXP_TAB_START 0x9008A400 #define CA_EXP_TAB_LEN 0x00000100 #define CA_VET_TAB_START 0x9008A500 #define CA_VET_TAB_LEN 0x00001000 MEMORY { /* MCU0_R5F_0 local view*/ #define DDR0_START (0x80000000) #define DDR0_RESERVED_SIZE (0x20000000) #define DDR0_MCUSW_SIZE (0x01000000) /* j7200 MCMS3 locations */ /* j7200 Reserved Memory for ARM Trusted Firmware */ MSMC3_ARM_FW (RWIX) : origin=0x70000000 length=0x40000 /* 256KB */ MSMC3 (RWIX) : origin=0x70040000 length=0xC0000 /* 8MB - 320KB */ /* j7200 Reserved Memory for DMSC Firmware */ MSMC3_DMSC_FW (RWIX) : origin=0x707F0000 length=0x10000 /* 64KB */ //DDR0_RESERVED (RWIX) : origin=DDR0_START length=DDR0_RESERVED_SIZE DDR0_MCUSW (RWIX) : origin=(DDR0_START + DDR0_RESERVED_SIZE) length=DDR0_MCUSW_SIZE MCU0_R5F_TCMA (X) : origin = 0x0 length=0x100 MCU0_R5F_TCMB0 (RWIX) : origin = 0x41010000 length=0x8000 MCU0_R5F_SBL_VECT : ORIGIN = 0x41C00000, LENGTH = 248k OCMRAM_SBL_SYSFW : ORIGIN = 0x41c3e000, LENGTH = 0x40000 OCMRAM_SBL_UNUSED : ORIGIN = 0x41c7f000, LENGTH = 0x1000 //VECTORS : ORIGIN = 0x701ff000, LENGTH = 0x1000 exceptiontable (X) : ORIGIN = 0x70100000, LENGTH = CA_EXP_TAB_LEN flash_rodata : ORIGIN = CA_CONST_DATA_START, LENGTH = CA_CONST_DATA_LEN /* constant variable area*/ rw_ram_prm_init : ORIGIN = CA_RAM_INIT_START, LENGTH = CA_RAM_INIT_LEN /* 8 KB For initialised variables*/ stack_ram : ORIGIN = CA_RAM_DATA_START, LENGTH = CA_RAM_DATA_LEN /* 8 KB For stack initialization*/ interrupttable (X) : ORIGIN = CA_VET_TAB_START, LENGTH = CA_VET_TAB_LEN flash_text : ORIGIN = CA_CODE_START, LENGTH = 248k /* program Code area*/ rw_ram_prm_noinit : ORIGIN = 0x9009A500, LENGTH = CA_RAM_NOINIT_LEN /* 8 KB For cleared variables*/ rw_ram_prm_clear : ORIGIN = CA_RAM_CLR_START, LENGTH = CA_RAM_CLR_LEN /* 8 KB For unspecified variables*/ //flash_text_end : ORIGIN = 0x700B8800, LENGTH = 4 /* program Code area*/ //userdefinedarea : ORIGIN = 0x01000000, LENGTH = 32k /* userdefined area*/ /* DDR0 (RWIX) : origin = 0x80000000 length = 0x80000000 */ /*------------------------------------------------------------*/ /*------------------------------------------------------------*/ } SECTIONS { .STARTUP align(4) >MCU0_R5F_TCMA /* start of exception interrupt */ .rstvectors align(4) >MCU0_R5F_SBL_VECT /* start of exception interrupt */ VECT align(16) >exceptiontable SYS align(4) >exceptiontable .inttable align(4) >interrupttable .inttable_end >interrupttable .sdata >rw_ram_prm_init .data >rw_ram_prm_init .zdata align(4) >rw_ram_prm_init .VAR_INIT_32 >rw_ram_prm_init .VAR_POWER_ON_INIT_32 >rw_ram_prm_init .VAR_FAST_INIT_32 >rw_ram_prm_init .VAR_INIT_16 >rw_ram_prm_init .VAR_POWER_ON_INIT_16 >rw_ram_prm_init .VAR_FAST_INIT_16 >rw_ram_prm_init .VAR_INIT_8 >rw_ram_prm_init .VAR_POWER_ON_INIT_8 >rw_ram_prm_init .VAR_FAST_INIT_8 >rw_ram_prm_init .VAR_INIT_BOOLEAN >rw_ram_prm_init .VAR_POWER_ON_INIT_BOOLEAN >rw_ram_prm_init .VAR_FAST_INIT_BOOLEAN >rw_ram_prm_init .VAR_INIT_UNSPECIFIED >rw_ram_prm_init .VAR_POWER_ON_INIT_UNSPECIFIED >rw_ram_prm_init .VAR_FAST_INIT_UNSPECIFIED >rw_ram_prm_init .sdabase align(4) >rw_ram_prm_noinit /* initialize globalpointer GP for SDA addressing */ .sbss >rw_ram_prm_noinit .bss >rw_ram_prm_noinit .zbss align(4) >rw_ram_prm_noinit .VAR_NO_INIT_32 >rw_ram_prm_noinit .EG_TEST_RESULT_32_SECTION >rw_ram_prm_noinit .VAR_SAVED_ZONE_32 >rw_ram_prm_noinit .VAR_FAST_NO_INIT_32 >rw_ram_prm_noinit .VAR_NO_INIT_16 >rw_ram_prm_noinit .VAR_SAVED_ZONE_16 >rw_ram_prm_noinit .VAR_FAST_NO_INIT_16 >rw_ram_prm_noinit .VAR_NO_INIT_8 >rw_ram_prm_noinit .VAR_SAVED_ZONE_8 >rw_ram_prm_noinit .VAR_FAST_NO_INIT_8 >rw_ram_prm_noinit .VAR_SAVED_ZONE_BOOLEAN >rw_ram_prm_noinit .VAR_NO_INIT_BOOLEAN >rw_ram_prm_noinit .VAR_NO_INIT_UNSPECIFIED_RAM >rw_ram_prm_noinit .VAR_NO_INIT_STACK_CORE1_UNSPECIFIED >rw_ram_prm_noinit .VAR_FAST_NO_INIT_BOOLEAN >rw_ram_prm_noinit .VAR_NO_INIT_UNSPECIFIED >rw_ram_prm_noinit .VAR_SAVED_ZONE_UNSPECIFIED >rw_ram_prm_noinit .VAR_FAST_NO_INIT_UNSPECIFIED >rw_ram_prm_noinit .VAR_CLEARED_32 align(4) >rw_ram_prm_clear .VAR_POWER_ON_CLEARED_32 >rw_ram_prm_clear .VAR_FAST_CLEARED_32 >rw_ram_prm_clear .VAR_CLEARED_16 >rw_ram_prm_clear .VAR_POWER_ON_CLEARED_16 >rw_ram_prm_clear .VAR_FAST_CLEARED_16 >rw_ram_prm_clear .VAR_CLEARED_8 >rw_ram_prm_clear .VAR_POWER_ON_CLEARED_8 >rw_ram_prm_clear .VAR_FAST_CLEARED_8 >rw_ram_prm_clear .VAR_CLEARED_BOOLEAN >rw_ram_prm_clear .VAR_POWER_ON_CLEARED_BOOLEAN >rw_ram_prm_clear .VAR_FAST_CLEARED_BOOLEAN >rw_ram_prm_clear .VAR_CLEARED_UNSPECIFIED >rw_ram_prm_clear .VAR_POWER_ON_CLEARED_UNSPECIFIED >rw_ram_prm_clear .VAR_FAST_CLEARED_UNSPECIFIED >rw_ram_prm_clear .ramtext align(128) >rw_ram_prm_clear /* initialized and zero-initialized data in TDA area */ .tdata align(4) >rw_ram_prm_clear /* initialized and zero-initialized data in TDA area */ .exec align(128) >rw_ram_prm_clear .stack >stack_ram .VAR_NO_INIT_STACK_UNSPECIFIED >stack_ram .heapbase align(4) >stack_ram .heap align(4) >stack_ram /* definition of heap size */ .VAR_NO_INIT_UNSPECIFIED_STACK >stack_ram .VAR_INIT_BOOLEAN_RAM >stack_ram /*------------------------------------------------------------*/ /* ROM SECTIONS */ /*------------------------------------------------------------*/ .APP_START align(256) >flash_text .fixaddr align(4) >flash_text /* ghs internal (compiler) */ .fixtype align(4) >flash_text /* ghs internal (compiler) */ .secinfo align(4) >flash_text /* ghs internal (runtime library) */ .syscall align(4) >flash_text /* ghs internal (linker) */ .text >flash_text .CODE align(4) >flash_text .CALLOUT_CODE align(4) >flash_text .OS_CODE align(4) >flash_text .cinit >flash_rodata .sysmem >flash_rodata /*Add constant data here*/ .rozdata align(4) >flash_rodata /* constant datas in ZDA area */ .robase align(4) >flash_rodata /* initialize textpointer TP for SDA addressing */ .rosdata align(4) >flash_rodata /* constant datas in SDA area */ .rodata align(4) >flash_rodata /* constant datas in normal area */ .bootCode >MSMC3 .startupCode >MSMC3 .startupData >MSMC3, type = NOINIT .CONST_32 >flash_rodata .CONST_16 >flash_rodata .CONST_8 >flash_rodata .const >flash_rodata .CONST_UNSPECIFIED >flash_rodata .CONST_BOOLEAN >flash_rodata .CONST_SAVED_RECOVERY_ZONE_16 >flash_rodata .CONST_SAVED_RECOVERY_ZONE_8 >flash_rodata .CONST_SAVED_RECOVERY_ZONE_32 >flash_rodata .CONST_SAVED_RECOVERY_ZONE_UNSPECIFIED >flash_rodata .CONST_SAVED_RECOVERY_ZONE_BOOLEAN >flash_rodata .CONFIG_DATA_8 >flash_rodata .CONFIG_DATA_16 >flash_rodata .CONFIG_DATA_32 >flash_rodata .CONFIG_DATA_BOOLEAN >flash_rodata .CONFIG_DATA_UNSPECIFIED >flash_rodata .CONFIG_CONST_UNSPECIFIED_ROM >flash_rodata .CONFIG_DATA_8_RAM >flash_rodata .CONFIG_DATA_UNSPECIFIED_RAM >flash_rodata .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) >stack_ram (HIGH) RUN_START(__IRQ_STACK_START) RUN_END(__IRQ_STACK_END) .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) >stack_ram (HIGH) RUN_START(__FIQ_STACK_START) RUN_END(__FIQ_STACK_END) .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) >stack_ram (HIGH) RUN_START(__ABORT_STACK_START) RUN_END(__ABORT_STACK_END) .undStack : {. = . + __UND_STACK_SIZE;} align(4) >stack_ram (HIGH) RUN_START(__UND_STACK_START) RUN_END(__UND_STACK_END) .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) >stack_ram (HIGH) RUN_START(__SVC_STACK_START) RUN_END(__SVC_STACK_END) /*Shared Memory*/ .APP_SHAREDMEMORY >DDR0_MCUSW /* Additional sections settings */ McalNoInitSection : fill=FILL_PATTERN, align=4, load > rw_ram_prm_noinit, type = NOINIT { .=align(4); __linker_can_no_init_start = .; . += FILL_LENGTH; *(CAN_DATA_NO_INIT_UNSPECIFIED_SECTION) *(CAN_DATA_NO_INIT_32_SECTION) .=align(4); . += FILL_LENGTH; __linker_can_no_init_end = .; .=align(4); __linker_gpt_no_init_start = .; . += FILL_LENGTH; *(GPT_DATA_NO_INIT_UNSPECIFIED_SECTION) .=align(4); . += FILL_LENGTH; __linker_gpt_no_init_end = .; } McalInitSection : fill=FILL_PATTERN, align=4, load > rw_ram_prm_init { .=align(4); __linker_gpt_init_start = .; . += FILL_LENGTH; *(GPT_DATA_INIT_32_SECTION) .=align(4); . += FILL_LENGTH; __linker_gpt_init_end = .; .=align(4); __linker_can_init_start = .; . += FILL_LENGTH; *(CAN_DATA_INIT_8_SECTION) .=align(4); . += FILL_LENGTH; __linker_can_init_end = .; } McalConstSection : fill=FILL_PATTERN, align=4, load > flash_rodata { .=align(4); __linker_dio_const_start = .; . += FILL_LENGTH; *(DIO_CONST_32_SECTION) *(DIO_CONST_UNSPECIFIED_SECTION) .=align(4); . += FILL_LENGTH; __linker_dio_const_end = .; .=align(4); __linker_can_const_start = .; . += FILL_LENGTH; *(CAN_CONST_8_SECTION) *(CAN_CONFIG_SECTION) .=align(4); . += FILL_LENGTH; __linker_can_const_end = .; .=align(4); __linker_gpt_const_start = .; . += FILL_LENGTH; *(GPT_CONST_32_SECTION) *(GPT_CONFIG_SECTION) .=align(4); . += FILL_LENGTH; __linker_gpt_const_end = .; } /* Additional sections settings */ McalTextSection : fill=FILL_PATTERN, align=4, load > flash_text { .=align(4); __linker_can_text_start = .; . += FILL_LENGTH; *(CAN_TEXT_SECTION) *(CAN_ISR_TEXT_SECTION) .=align(4); . += FILL_LENGTH; __linker_can_text_end = .; .=align(4); __linker_dio_text_start = .; . += FILL_LENGTH; *(DIO_TEXT_SECTION) .=align(4); . += FILL_LENGTH; __linker_dio_text_end = .; .=align(4); __linker_gpt_text_start = .; . += FILL_LENGTH; *(GPT_TEXT_SECTION) *(GPT_ISR_TEXT_SECTION) .=align(4); . += FILL_LENGTH; __linker_gpt_text_end = .; } }