static Board_STATUS Board_CfgMultilinkSgmiiXaui(void)
{
	CSL_SerdesResult result;
	uint32_t laneNum;
    CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
    CSL_SerdesLaneEnableParams serdesLane0EnableParams  = {0};
	CSL_SerdesLaneEnableParams serdesLane1EnableParams  = {0};
	CSL_SerdesMultilink multiLinkId = CSL_SERDES_USXGMII_SGMII_MULTILINK;
	CSL_SerdesInstance serdesInstanceId = CSL_TORRENT_SERDES1;

    memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));
	memset(&serdesLane1EnableParams, 0, sizeof(serdesLane1EnableParams));

    serdesLane0EnableParams.serdesInstance    = (CSL_SerdesInstance)CSL_TORRENT_SERDES1;
    serdesLane0EnableParams.baseAddr          = CSL_WIZ16B8M4CT3_1_WIZ16B8M4CT3_BASE;
    serdesLane0EnableParams.refClock          = CSL_SERDES_REF_CLOCK_156p25M;
    serdesLane0EnableParams.refClkSrc         = CSL_SERDES_REF_CLOCK_INT0;
    serdesLane0EnableParams.numLanes          = 2;
    serdesLane0EnableParams.laneMask          = 0xc;
    serdesLane0EnableParams.SSC_mode          = CSL_SERDES_NO_SSC;
    serdesLane0EnableParams.phyType           = CSL_SERDES_PHY_TYPE_USXGMII;
    serdesLane0EnableParams.operatingMode     = CSL_SERDES_FUNCTIONAL_MODE;
    serdesLane0EnableParams.phyInstanceNum    = 0;
    serdesLane0EnableParams.pcieGenType       = CSL_SERDES_PCIE_GEN4;
    serdesLane0EnableParams.linkRate          = CSL_SERDES_LINK_RATE_5p15625G;
	
	for(laneNum=0;laneNum<CSL_SERDES_MAX_LANES;laneNum++)
	{
		if ((serdesLane0EnableParams.laneMask & (1<<laneNum))!=0)
		{
			serdesLane0EnableParams.laneCtrlRate[laneNum] = CSL_SERDES_LANE_FULL_RATE;
			serdesLane0EnableParams.loopbackMode[laneNum] = CSL_SERDES_LOOPBACK_DISABLED;
		}
	}
	
	
    serdesLane1EnableParams.serdesInstance    = (CSL_SerdesInstance)CSL_TORRENT_SERDES1;
    serdesLane1EnableParams.baseAddr          = CSL_WIZ16B8M4CT3_1_WIZ16B8M4CT3_BASE;
    serdesLane1EnableParams.refClock          = CSL_SERDES_REF_CLOCK_100M;
    serdesLane1EnableParams.refClkSrc         = CSL_SERDES_REF_CLOCK_INT1;
    serdesLane1EnableParams.linkRate          = CSL_SERDES_LINK_RATE_1p25G;
    serdesLane1EnableParams.numLanes          = 2;
    serdesLane1EnableParams.laneMask          = 0x3;
    serdesLane1EnableParams.SSC_mode          = CSL_SERDES_NO_SSC;
    serdesLane1EnableParams.phyType           = CSL_SERDES_PHY_TYPE_SGMII;
    serdesLane1EnableParams.operatingMode     = CSL_SERDES_FUNCTIONAL_MODE;
    serdesLane1EnableParams.phyInstanceNum    = 0;
    serdesLane1EnableParams.pcieGenType       = CSL_SERDES_PCIE_GEN3;

	for(laneNum=0;laneNum<CSL_SERDES_MAX_LANES;laneNum++)
	{
		if ((serdesLane1EnableParams.laneMask & (1<<laneNum))!=0)
		{
			serdesLane1EnableParams.laneCtrlRate[laneNum] = CSL_SERDES_LANE_FULL_RATE;
			serdesLane1EnableParams.loopbackMode[laneNum] = CSL_SERDES_LOOPBACK_DISABLED;
		}
	}
	
    /* End: Serdes-1: Lane 0,1 (MAC Port 3,4 : SGMII) Lane 2,3 (MAC Port 1,2 : USXGMII) */

    CSL_serdesPorReset(serdesLane0EnableParams.baseAddr);

    /* Select the IP type, IP instance num, Serdes Lane Number */
    CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
        serdesLane0EnableParams.phyType,
        serdesLane0EnableParams.phyInstanceNum,
        serdesLane0EnableParams.serdesInstance,
        2);
	
    CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
		serdesLane0EnableParams.phyType,
		serdesLane0EnableParams.phyInstanceNum,
		serdesLane0EnableParams.serdesInstance,
		3);
	
	CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
		serdesLane1EnableParams.phyType,
		serdesLane1EnableParams.phyInstanceNum,
		serdesLane1EnableParams.serdesInstance,
		0);
	
	CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
		serdesLane1EnableParams.phyType,
		serdesLane1EnableParams.phyInstanceNum,
		serdesLane1EnableParams.serdesInstance,
		1);	

    result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,
                                 serdesLane0EnableParams.baseAddr,
                                 serdesLane0EnableParams.refClock,
                                 serdesLane0EnableParams.refClkSrc,
                                 serdesLane0EnableParams.serdesInstance,
                                 serdesLane0EnableParams.phyType);
	
	if (result != CSL_SERDES_NO_ERR)
    {
        return BOARD_FAIL;
    }

    result = CSL_serdesRefclkSel1(CSL_CTRL_MMR0_CFG0_BASE,
                                 serdesLane1EnableParams.baseAddr,
                                 serdesLane1EnableParams.refClock,
                                 serdesLane1EnableParams.refClkSrc,
                                 serdesLane1EnableParams.serdesInstance,
                                 serdesLane1EnableParams.phyType);

    if (result != CSL_SERDES_NO_ERR)
    {
        return BOARD_FAIL;
    }

    /* Load the Serdes Config File */
       result = CSL_serdesMultiLinkInit(multiLinkId,
                                     serdesInstanceId,
                                     &serdesLane0EnableParams,
                                     &serdesLane1EnableParams);

    /* Return error if input params are invalid */
    if (result != CSL_SERDES_NO_ERR)
    {
        return BOARD_FAIL;
    }

    /* Common Lane Enable API for lane enable, pll enable etc */
    /* Common Lane Enable API for lane enable, pll enable etc */
    for(laneNum=0;laneNum<CSL_SERDES_MAX_LANES;laneNum++)
    {
        if ((serdesLane0EnableParams.laneMask & (1<<laneNum))!=0)
        {
            CSL_serdesEnableLanes(serdesLane0EnableParams.baseAddr, laneNum, serdesLane0EnableParams.phyType, serdesLane0EnableParams.linkRate, serdesLane0EnableParams.operatingMode);
        }
    }

    for(laneNum=0;laneNum<CSL_SERDES_MAX_LANES;laneNum++)
    {
        if ((serdesLane1EnableParams.laneMask & (1<<laneNum))!=0)
        {
            CSL_serdesEnableLanes(serdesLane1EnableParams.baseAddr, laneNum, serdesLane1EnableParams.phyType, serdesLane1EnableParams.linkRate, serdesLane1EnableParams.operatingMode);
        }
    }

    /* Release PHY Reset*/
    CSL_serdesReleaseReset(serdesLane0EnableParams.baseAddr);
	
	return BOARD_SOK;
}



>> CSL_FINSR(*(volatile uint32_t *)(&torrent_sds_reg->PMA_RX_LANE_REGISTERS[3].RX_DIAG_DFE_AMP_TUNE_3__RX_DIAG_DFE_AMP_TUNE_2),15,0,(uint32_t)0x0C01);//USXGMII
   CSL_FINSR(*(volatile uint32_t *)(&torrent_sds_reg->PMA_RX_LANE_REGISTERS[3].RX_DIAG_DFE_AMP_TUNE_3__RX_DIAG_DFE_AMP_TUNE_2),15,0,(uint32_t)0x0C21);//USXGMII