1 spi0_pins: pinmux_spi0 {
  2     pinctrl-single,pins = <
  3         0x150 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */
  4         0x15C (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
  5         0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */
  6         0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
  7         0x160 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs1.spi0_cs1 */
  8     >;
  9 };
10
11
12 /* SPI Busses */
13 &spi0 {
14     status = "okay";
15     pinctrl-names = "default";
16     pinctrl-0 = <&spi0_pins>;
17
18     m25p80@0 {
19         compatible = "mx25l6405d";
20         spi-max-frequency = <40000000>;
21
22         reg = <0>;
23         spi-cpol;
24         spi-cpha;
25         #address-cells = <1>;
26         #size-cells = <1>;
27
28         /* reg : The partition's offset and size within the mtd bank. */
29         partitions@0 {
30             label = "MLO";
31             reg = <0x0 0x80000>;
32         };
33
34         partitions@1 {
35             label = "U-Boot";
36             reg = <0x80000 0x100000>;
37         };
38
39         partitions@2 {
40             label = "U-Boot Env";
41             reg = <0x180000 0x20000>;
42         };
43
44     };
45
46     tpm_spi_tis@1{
47         compatible = "infineon,slb9670";
48         reg = <1>;  /* CE1 */
49         spi-max-frequency = <500000>;
50     };
51
52 };