[BEGIN] 2024/11/13 17:42:02 TDCU4@QNX:/# U-Boot SPL 2021.01 (Jul 12 2024 - 15:16:01 +0800) Model: TDCU4 R5 UB.R6.001 BW 4G ti_sci system-controller@44083000: Message not acknowledgedti_sci system-controller@44083000: Message not acknowledgedSYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.3--1-g2249f (Chill Capybara') SPL initial stack usage: 13472 bytes BOARD_ID: 10 Trying to boot from MMC1 Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted init_env from device 17 not supported! Starting ATF on ARM64 core... U-Boot SPL 2021.01 (Jul 12 2024 - 15:15:52 +0800) Model: TDCU4 UB.R6.001 4G ti_sci system-controller@44083000: Message not acknowledgedti_sci system-controller@44083000: Message not acknowledgedSYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.3--1-g2249f (Chill Capybara') BOARD_ID: 10 Trying to boot from MMC1 U-Boot 2021.01 (Jul 12 2024 - 15:15:52 +0800) SoC: J721S2 SR1.0 GP Model: TDCU4 UB.R6.001 4G Board: TDCU4 U-Boot version: UB.006 BOARD_ID: 10 DRAM: 4 GiB Flash: 0 Bytes MMC: mmc@4f80000: 0, mmc@4fb0000: 1 Loading Environment from MMC... OK In: serial@2890000 Out: serial@2890000 Err: serial@2890000 am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA02102 cpsw_ver: 0x6BA82102 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000 FRU Version: 2 FRU Header: ee3355aa BI Header: eeaa5511 PI Header: 57f3f586 Manufacturer: Foxconn Industrial Internet Board PROD DT: 2024/09/23 Board Name: TDCU4 Board Version: X07 Board PN: 1A7277700-600-G Board SN: 1A7277700X0749R00B GPIO0_27: 0 GPIO0_30: 1 ENV boot_partition=A Net: Could not get PHY for ethernet@46000000port@1: addr 10 am65_cpsw_nuss_port ethernet@46000000port@1: phy_connect() failed No ethernet found. Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc0(part 0) is current device SD/MMC found on device 0 Failed to load 'boot.scr' Failed to load 'uEnv.txt' 10 bytes read in 5 ms (2 KiB/s) Base Address: 0x82000000 10 bytes written in 5 ms (2 KiB/s) Checked Boot File System Running uenvcmd ... k3_r5f_rproc r5f@41000000: Core 1 is already in use. No rproc commands work k3_r5f_rproc r5f@41400000: Core 2 is already in use. No rproc commands work 1010792 bytes read in 20 ms (48.2 MiB/s) Load Remote Processor 2 with data@addr=0x82000000 1010792 bytes: Success! 297868 bytes read in 31 ms (9.2 MiB/s) Load Remote Processor 3 with data@addr=0x82000000 297868 bytes: Success! Failed to load '/lib/firmware/j721s2-main-r5f1_0-fw' Failed to load '/lib/firmware/j721s2-main-r5f1_1-fw' 14815240 bytes read in 71 ms (199 MiB/s) Load Remote Processor 6 with data@addr=0x82000000 14815240 bytes: Success! 9760640 bytes read in 74 ms (125.8 MiB/s) Load Remote Processor 7 with data@addr=0x82000000 9760640 bytes: Success! 11621256 bytes read in 89 ms (124.5 MiB/s) ## Starting application at 0x80080000 ... BOARD_ID: 10 MMU: 16-bit ASID 44-bit PA TCR_EL1=b5183519 ARM GIC-500 r1p1, arch v3.0 detected gic_v3_lpi_add_entry for vectors 8192 -> 8447, Ok gic_v3_lpi_add_entry for vectors 8448 -> 65535, Ok No SPI intrinfo. Add default entry for 32 -> 991 vectors, Ok LPI config table #1 @ 000000008000f000, callout vaddr: ffffff8040251000 aarch64_cpuspeed: core speed 2000 cpu0: MPIDR=80000000 cpu0: MIDR=411fd080 Cortex-A72 r1p0 cpu0: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT cpu0: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu0: L1 Icache 48K linesz=64 set/way=256/3 cpu0: L1 Dcache 32K linesz=64 set/way=256/2 cpu0: L2 Unified 1024K linesz=64 set/way=1024/16 Enabling ITS 0 ITS queue at 0000000080020000, num slots: 256 Issue MAPC/SYNC/INVALL commands for ICID 0 update CWRITER to 0x00000060 Waiting for all commands to be processed ... Done in 1 tries Enable LPIs in GICR_CTLR @ 0000000001900000 for CPU0 Display set to A72 Total Available L3 cache (MSMC SRAM): 4194304 bytes Loading IFS...decompressing...done aarch64_cpuspeed: core speed 2000 cpu1: MPIDR=80000001 cpu1: MIDR=411fd080 Cortex-A72 r1p0 cpu1: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT cpu1: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu1: L1 Icache 48K linesz=64 set/way=256/3 cpu1: L1 Dcache 32K linesz=64 set/way=256/2 cpu1: L2 Unified 1024K linesz=64 set/way=1024/16 ITS 0 already Enabled ITS queue at 0000000080020000, num slots: 256 Issue MAPC/SYNC/INVALL commands for ICID 1 update CWRITER to 0x000000c0 Waiting for all commands to be processed ... Done in 1 tries Enable LPIs in GICR_CTLR @ 0000000001920000 for CPU1 System page at phys:0000000080023000 user:ffffff8040275000 kern:ffffff8040272000 Starting next program at vffffff8060087300 All ClockCycles offsets within tolerance Welcome to QNX Neutrino 7.1.0 on the TDCU4-CD Board!! Starting random service ... start serial driver start i2c driver Starting MMC/SD memory card driver... eMMC Starting MMC/SD memory card driver... SD Setting environment variables... done.. Mounting the emmc .. Path=0 - am65x target=0 lun=0 Direct-Access(0) - SDMMC: DG4008 Rev: 0.1 Booting to qnxfs_a mount /dev/emmc0.ms.4 Mounting OTA and Userdata directory ... Looking for user script to run: /ti_fs/scripts/user.sh Running user script... user.sh called... Setting additional environment variables... Version: QNX.R5.008 Starting tisci-mgr.. Starting shmemallocator.. Starting tiipc-mgr.. Mounting OTA and Userdata directory Done Starting tiudma-mgr.. force change GTC CLK to 200M |--------------------------------------------------------------------------------| | VERSION INFO | |--------------------------------------------------------------------------------| | K3CONF | QNX (version v1.0.5-137-gc1339e23d built Tue Nov 5 01:10:35 UTC 2024) | | SoC | J721S2 SR1.0 | | SYSFW | ABI: 3.1 (firmware version 0x0008 '8.6.3--1-g2249f (Chill Capybara)') | |--------------------------------------------------------------------------------| |------------------------------------------------------------------------------------------------------------------------------| | Device ID | Clock ID | Clock Name | Status | Clock Frequency | |------------------------------------------------------------------------------------------------------------------------------| | 61 | 0 | DEV_GTC0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 61 | 1 | DEV_GTC0_GTC_CLK | CLK_STATE_READY | 200000000 | | 61 | 2 | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 61 | 3 | DEV_GTC0_GTC_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | 61 | 4 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 61 | 5 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 61 | 6 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 61 | 7 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 61 | 8 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 61 | 9 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 61 | 10 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | 61 | 11 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | 61 | 16 | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | 61 | 17 | DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | |------------------------------------------------------------------------------------------------------------------------------| force change CPSW_CPTS_RFT_CLK to 500M |--------------------------------------------------------------------------------| | VERSION INFO | |--------------------------------------------------------------------------------| | K3CONF | QNX (version v1.0.5-137-gc1339e23d built Tue Nov 5 01:10:35 UTC 2024) | | SoC | J721S2 SR1.0 | | SYSFW | ABI: 3.1 (firmware version 0x0008 '8.6.3--1-g2249f (Chill Capybara)') | |--------------------------------------------------------------------------------| |------------------------------------------------------------------------------------------------------------------------------------| | Device ID | Clock ID | Clock Name | Status | Clock Frequency | |------------------------------------------------------------------------------------------------------------------------------------| | 28 | 0 | DEV_CPSW1_MDIO_MDCLK_O | CLK_STATE_READY | 0 | | 28 | 1 | DEV_CPSW1_CPTS_GENF0 | CLK_STATE_READY | 0 | | 28 | 3 | DEV_CPSW1_CPTS_RFT_CLK | CLK_STATE_READY | 500000000 | | 28 | 4 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | 28 | 5 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | 28 | 6 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 28 | 7 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 28 | 8 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 28 | 9 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 28 | 10 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 28 | 11 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 28 | 12 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | 28 | 13 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | 28 | 18 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | 28 | 19 | DEV_CPSW1_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | 28 | 20 | DEV_CPSW1_GMII1_MR_CLK | CLK_STATE_READY | 25000000 | | 28 | 21 | DEV_CPSW1_GMII_RFT_CLK | CLK_STATE_READY | 125000000 | | 28 | 22 | DEV_CPSW1_RGMII1_RXC_I | CLK_STATE_READY | 0 | | 28 | 26 | DEV_CPSW1_RMII_MHZ_50_CLK | CLK_STATE_READY | 0 | | 28 | 27 | DEV_CPSW1_RGMII1_TXC_O | CLK_STATE_READY | 0 | | 28 | 28 | DEV_CPSW1_CPPI_CLK_CLK | CLK_STATE_READY | 320000000 | | 28 | 29 | DEV_CPSW1_RGMII_MHZ_5_CLK | CLK_STATE_READY | 5000000 | | 28 | 30 | DEV_CPSW1_GMII1_MT_CLK | CLK_STATE_READY | 25000000 | | 28 | 32 | DEV_CPSW1_RGMII_MHZ_50_CLK | CLK_STATE_READY | 50000000 | | 28 | 33 | DEV_CPSW1_RGMII_MHZ_250_CLK | CLK_STATE_READY | 250000000 | |------------------------------------------------------------------------------------------------------------------------------------| make ota_agent default folder mkdir: /ota/agent: File exists Starting Network driver... Starting sshd Configuring IP Address... OTA is not running, wake up ota agent /ti_fs/etc/ota_agent.sh[12]: /ti_fs/usr/bin/ota_agent: cannot execute - No such file or directory Looking for camera script to run: /ti_fs/vision_apps/boot_auto_run_camera_360.sh done... TDCU4@QNX:/# Process 180239 (io-pkt-v4-hc) terminated SIGBUS code=3 fltno=6 ip=00000051608af7fc(/proc/boot/libc.so.5@pthread_mutex_unlock+0x0000000000000044) mapaddr=00000000000367fc. [END] 2024/11/13 17:44:08