../ti_components/drivers/pdk_01_10_03_07/packages/ti/drv/vps/src/vpslib/hal/src/vpshal_isscal.c /**************************************************************************************/ static int32_t CalSetVportCfg(const isshalCalInstObj_t *pInst, const vpsissCalVPort_t *cfg, uint32_t cportId) { uint32_t baseAddr; volatile uint32_t reg; GT_assert(VpsHalTrace, (NULL != pInst)); GT_assert(VpsHalTrace, (NULL != cfg)); baseAddr = pInst->baseAddr; GT_assert(VpsHalTrace, (0U != baseAddr)); reg = HW_RD_REG32(baseAddr + CAL_VPORT_CTRL1); reg &= ~CAL_VPORT_CTRL1_PCLK_MASK; if((uint32_t)TRUE == cfg->enable) { reg &= ~(CAL_VPORT_CTRL1_XBLK_MASK | CAL_VPORT_CTRL1_YBLK_MASK | CAL_VPORT_CTRL1_WIDTH_MASK); reg |= CAL_VPORT_CTRL1_PCLK_MASK & cfg->pixClock; reg |= CAL_VPORT_CTRL1_XBLK_MASK & (cfg->xBlk << CAL_VPORT_CTRL1_XBLK_SHIFT); reg |= CAL_VPORT_CTRL1_YBLK_MASK & (cfg->yBlk << CAL_VPORT_CTRL1_YBLK_SHIFT); if(0x0U != cfg->width) { reg |= CAL_VPORT_CTRL1_WIDTH_MASK; } HW_WR_REG32(baseAddr + CAL_VPORT_CTRL1, reg); reg = HW_RD_REG32(baseAddr + CAL_VPORT_CTRL2); reg &= ~(CAL_VPORT_CTRL2_RDY_THR_MASK | CAL_VPORT_CTRL2_FSM_RESET_MASK | CAL_VPORT_CTRL2_FS_RESETS_MASK | CAL_VPORT_CTRL2_FREERUNNING_MASK | CAL_VPORT_CTRL2_CPORT_MASK); reg |= CAL_VPORT_CTRL2_CPORT_MASK & cportId; if((uint32_t)TRUE == cfg->freeRun) { reg |= CAL_VPORT_CTRL2_FREERUNNING_MASK; } if((uint32_t)TRUE == cfg->fsReset) { reg |= CAL_VPORT_CTRL2_FS_RESETS_MASK; } reg |= CAL_VPORT_CTRL2_RDY_THR_MASK & (cfg->rdyThr << CAL_VPORT_CTRL2_RDY_THR_SHIFT); /* Enable transmission on vports 2, 3 & 4 */ reg = reg | 0x20U; /* Configure the cport ID's */ reg = reg | 0x01U; HW_WR_REG32(baseAddr + CAL_VPORT_CTRL2, reg); } else { HW_WR_REG32(baseAddr + CAL_VPORT_CTRL1, reg); } return FVID2_SOK; } !!!!!!! see Write2VIP ../vision_sdk/links_fw/src/rtos/links_ipu/iss_capture/issCaptureLink_drv.c /**************************************************************************************/ Void IssCaptureLink_drvSetDrvCfg(IssCaptureLink_Obj *pObj) { Vps_CaptCreateParams *drvCreatePrms; vpsissCalCmplxIoCfg_t *drvCmplxIoCfg; IssCaptureLink_Csi2Params *csi2Params; vpsissCalCfg_t *drvCalCfg; IssCaptureLink_OutParams *outPrms; UInt32 strmId, cmplxIoId, numPixProcUsed; drvCreatePrms = &pObj->drvCreatePrms; Fvid2CbParams_init(&pObj->drvCbPrms); VpsCaptCreateParams_init(drvCreatePrms); vpsissCalCfg_t_init(&pObj->drvCalCfg); pObj->drvInstId = VPS_CAPT_INST_ISS_CAL_A; pObj->drvCbPrms.cbFxn = &issCaptDrvCallback; pObj->drvCbPrms.appData = pObj; drvCreatePrms->videoIfMode = pObj->createArgs.videoIfMode; drvCreatePrms->videoIfWidth = pObj->createArgs.videoIfWidth; drvCreatePrms->bufCaptMode = pObj->createArgs.bufCaptMode; drvCreatePrms->numCh = 1U; /* CAL Treats channels as streams with in CAL */ drvCreatePrms->numStream = pObj->createArgs.numCh; drvCreatePrms->pAdditionalArgs = &pObj->drvIssCaptureCreatePrms; for (strmId = 0U; strmId < pObj->createArgs.numCh; strmId++) { drvCreatePrms->chNumMap[strmId][0U] = Vps_captMakeChNum(pObj->drvInstId, strmId, 0U); } memset(&pObj->drvIssCaptureCreatePrms, (Int32) 0, sizeof(pObj->drvIssCaptureCreatePrms)); pObj->drvCalCfg.numStream = pObj->createArgs.numCh; numPixProcUsed = 0U; for (strmId = 0U; strmId < pObj->createArgs.numCh; strmId++) { drvCalCfg = &pObj->drvCalCfg; outPrms = &pObj->createArgs.outParams[strmId]; drvCalCfg->streamId[strmId] = strmId; drvCalCfg->inFmt[strmId].width = outPrms->width; drvCalCfg->inFmt[strmId].height = outPrms->height; drvCalCfg->inFmt[strmId].pitch[0U] = pObj->info.queInfo[0].chInfo[strmId].pitch[0]; drvCalCfg->inFmt[strmId].bpp = outPrms->outBpp; drvCalCfg->inFmt[strmId].dataFormat = 0U; drvCalCfg->writeToMem[strmId] = (UInt32)TRUE; drvCalCfg->streamType[strmId] = VPS_ISS_CAL_TAG_PIX_DATA; drvCalCfg->isPixProcCfgValid[strmId] = (UInt32)FALSE; drvCalCfg->isBysOutCfgValid[strmId] = (UInt32)FALSE; drvCalCfg->bysInEnable[strmId] = (UInt32)FALSE; drvCalCfg->isVportCfgValid[strmId] = (UInt32)FALSE; if(SYSTEM_VIFM_SCH_CPI == pObj->createArgs.videoIfMode) { UTILS_assert(0U == strmId); drvCreatePrms->numCh = 1U; pObj->drvIssCaptureCreatePrms.subModules[strmId] = VPS_ISS_CAPT_CAL_SUB_CPORT_ID | VPS_ISS_CAPT_CAL_SUB_DMA_WR_ID | VPS_ISS_CAPT_CAL_SUB_DPCM_ENC_ID | VPS_ISS_CAPT_CAL_SUB_PIX_PACK_ID | VPS_ISS_CAPT_CAL_SUB_BYS_IN_ID; drvCalCfg->bysInEnable[strmId] = (UInt32)TRUE; if(pObj->createArgs.videoIfWidth == SYSTEM_VIFW_10BIT) { drvCalCfg->csi2DataFormat[strmId] = VPS_ISS_CAL_CSI2_RAW10; } else if(pObj->createArgs.videoIfWidth == SYSTEM_VIFW_12BIT) { drvCalCfg->csi2DataFormat[strmId] = VPS_ISS_CAL_CSI2_RAW12; } else if(pObj->createArgs.videoIfWidth == SYSTEM_VIFW_14BIT) { drvCalCfg->csi2DataFormat[strmId] = VPS_ISS_CAL_CSI2_RAW14; } else { drvCalCfg->csi2DataFormat[strmId] = VPS_ISS_CAL_CSI2_RAW12; } } else if(SYSTEM_VIFM_SCH_CSI2 == pObj->createArgs.videoIfMode) { pObj->drvIssCaptureCreatePrms.subModules[strmId] = VPS_ISS_CAPT_CAL_SUB_CSI2_ID | VPS_ISS_CAPT_CAL_SUB_CPORT_ID | VPS_ISS_CAPT_CAL_SUB_DMA_WR_ID | VPS_ISS_CAPT_CAL_SUB_PIX_EXTRACT_ID | VPS_ISS_CAPT_CAL_SUB_DPCM_DEC_ID | VPS_ISS_CAPT_CAL_SUB_DPCM_ENC_ID | VPS_ISS_CAPT_CAL_SUB_PIX_PACK_ID; if (0U == outPrms->phyInstance) { pObj->drvIssCaptureCreatePrms.subModules[strmId] |= VPS_ISS_CAPT_CAL_SUB_PPI_ID_0; drvCalCfg->cmplxIoId[strmId] = 0U; } else if (1U == outPrms->phyInstance) { pObj->drvIssCaptureCreatePrms.subModules[strmId] |= VPS_ISS_CAPT_CAL_SUB_PPI_ID_1; drvCalCfg->cmplxIoId[strmId] = 1U; } else { /* Illelagl PHY instance ID */ UTILS_assert((Bool) 0U); } drvCalCfg->csi2DataFormat[strmId] = (vpsissCalCsi2DataFormat) outPrms->inCsi2DataFormat; } else { /* Illegal interface */ UTILS_assert((Bool) 0U); } drvCalCfg->csi2VirtualChanNo[strmId] = outPrms->inCsi2VirtualChanNum; if (SYSTEM_BPP_BITS12_PACKED_MIPI == drvCalCfg->inFmt[strmId].bpp) { drvCalCfg->isPixProcCfgValid[strmId] = (UInt32)FALSE; /* These modules are not required */ pObj->drvIssCaptureCreatePrms.subModules[strmId] &= (UInt32) (~ (VPS_ISS_CAPT_CAL_SUB_PIX_EXTRACT_ID | VPS_ISS_CAPT_CAL_SUB_DPCM_DEC_ID | VPS_ISS_CAPT_CAL_SUB_DPCM_ENC_ID | VPS_ISS_CAPT_CAL_SUB_PIX_PACK_ID)); drvCalCfg->inFmt[strmId].width = (drvCalCfg->inFmt[strmId].width * 3u) / 2u; } else { drvCalCfg->isPixProcCfgValid[strmId] = (UInt32)TRUE; } drvCalCfg->pixProcCfg[strmId].decCodec = VPS_ISS_CAL_DPCM_DEC_BYPASS; drvCalCfg->pixProcCfg[strmId].enableDpcmInitContext = (UInt32)FALSE; drvCalCfg->pixProcCfg[strmId].encCodec = VPS_ISS_CAL_DPCM_ENC_BYPASS; drvCalCfg->pixProcCfg[strmId].pack = VPS_ISS_CAL_PIX_PACK_B16; if (((UInt32) TRUE == drvCalCfg->isPixProcCfgValid[strmId]) && (VPS_ISS_CAL_MAX_PIX_PROC_CONTEXT <= numPixProcUsed)) { drvCalCfg->isPixProcCfgValid[strmId] = FALSE; pObj->drvIssCaptureCreatePrms.subModules[strmId] &= (UInt32) (~ (VPS_ISS_CAPT_CAL_SUB_PIX_EXTRACT_ID | VPS_ISS_CAPT_CAL_SUB_DPCM_DEC_ID | VPS_ISS_CAPT_CAL_SUB_DPCM_ENC_ID | VPS_ISS_CAPT_CAL_SUB_PIX_PACK_ID)); Vps_printf(" ISSCAPTURE: Warning: Available pixel processing " "contexts is %d, " "Turning OFF pixel processing contexts for streams %d \n", VPS_ISS_CAL_MAX_PIX_PROC_CONTEXT, strmId); } if (outPrms->Write2VIP) { drvCalCfg->writeToMem[strmId] = FALSE; // pObj->drvIssCaptureCreatePrms.subModules[strmId] &=(UInt32)(~VPS_ISS_CAPT_CAL_SUB_DMA_WR_ID); // pObj->drvIssCaptureCreatePrms.subModules[strmId] |= VPS_ISS_CAPT_CAL_SUB_VPORT_ID; // pObj->drvIssCaptureCreatePrms.subModules[strmId] = VPS_ISS_CAPT_CAL_SUB_CSI2_ID | // VPS_ISS_CAPT_CAL_SUB_CPORT_ID | // VPS_ISS_CAPT_CAL_SUB_VPORT_ID; // drvCalCfg->isPixProcCfgValid[strmId] = (UInt32)FALSE; drvCalCfg->writeToMem[strmId] = (UInt32)FALSE; drvCalCfg->isVportCfgValid[strmId] = (UInt32)TRUE; drvCalCfg->vportCfg[strmId].enable = (UInt32)TRUE; drvCalCfg->vportCfg[strmId].pixClock = 20480U; drvCalCfg->vportCfg[strmId].width = 0U; drvCalCfg->vportCfg[strmId].xBlk = 0x4U; drvCalCfg->vportCfg[strmId].yBlk = 0x3CU; drvCalCfg->vportCfg[strmId].rdyThr = 0U; drvCalCfg->vportCfg[strmId].fsReset = TRUE; // drvCalCfg->vportCfg[strmId].freeRun = TRUE; // drvCalCfg->isPixProcCfgValid[strmId] = TRUE; // drvCalCfg->pixProcCfg[strmId].decCodec = VPS_ISS_CAL_DPCM_DEC_BYPASS; // drvCalCfg->pixProcCfg[strmId].enableDpcmInitContext = FALSE; // drvCalCfg->pixProcCfg[strmId].encCodec = VPS_ISS_CAL_DPCM_ENC_BYPASS; // drvCalCfg->pixProcCfg[strmId].pack = VPS_ISS_CAL_PIX_PACK_B16; } switch((System_Csi2DataFormat)(drvCalCfg->csi2DataFormat[strmId])) { case SYSTEM_CSI2_RAW10: drvCalCfg->pixProcCfg[strmId].extract = VPS_ISS_CAL_PIX_EXRCT_B10_MIPI; if (((SYSTEM_DF_YUV422I_UYVY == outPrms->outDataFormat) || ((SYSTEM_DF_YUV422I_YUYV == outPrms->outDataFormat))) || ((SYSTEM_DF_YUV422I_YVYU == outPrms->outDataFormat) || ((SYSTEM_DF_YUV422I_VYUY == outPrms->outDataFormat)))) { drvCalCfg->pixProcCfg[strmId].extract = VPS_ISS_CAL_PIX_EXRCT_B8; drvCalCfg->pixProcCfg[strmId].pack = VPS_ISS_CAL_PIX_PACK_B8; } break; case SYSTEM_CSI2_RAW12: //drvCalCfg->pixProcCfg[strmId].extract = VPS_ISS_CAL_PIX_EXRCT_B12_MIPI; // drvCalCfg->pixProcCfg[strmId].extract = VPS_ISS_CAL_PIX_EXRCT_B16_LE; drvCalCfg->pixProcCfg[strmId].extract = VPS_ISS_CAL_PIX_EXRCT_B12_MIPI; drvCalCfg->pixProcCfg[strmId].pack = VPS_ISS_CAL_PIX_PACK_B12_MIPI; break; case SYSTEM_CSI2_RAW14: drvCalCfg->pixProcCfg[strmId].extract = VPS_ISS_CAL_PIX_EXRCT_B14_MIPI; break; case SYSTEM_CSI2_RAW8: drvCalCfg->pixProcCfg[strmId].extract = VPS_ISS_CAL_PIX_EXRCT_B8; drvCalCfg->pixProcCfg[strmId].pack = VPS_ISS_CAL_PIX_PACK_B8; break; case SYSTEM_CSI2_YUV420_8B: case SYSTEM_CSI2_YUV420_8B_LEGACY: case SYSTEM_CSI2_YUV420_8B_CHROMA_SHIFT: case SYSTEM_CSI2_YUV422_8B: drvCalCfg->pixProcCfg[strmId].extract = VPS_ISS_CAL_PIX_EXRCT_B16_LE; drvCalCfg->pixProcCfg[strmId].pack = VPS_ISS_CAL_PIX_PACK_B16; // drvCalCfg->pixProcCfg[strmId].extract = VPS_ISS_CAL_PIX_EXRCT_B8; // drvCalCfg->pixProcCfg[strmId].pack = VPS_ISS_CAL_PIX_PACK_B8; break; // case SYSTEM_CSI2_YUV420_8B: // case SYSTEM_CSI2_YUV420_8B_LEGACY: // case SYSTEM_CSI2_YUV420_8B_CHROMA_SHIFT: // case SYSTEM_CSI2_YUV422_8B: // drvCalCfg->pixProcCfg[strmId].extract = VPS_ISS_CAL_PIX_EXRCT_B8; // drvCalCfg->pixProcCfg[strmId].pack = VPS_ISS_CAL_PIX_PACK_B8; // break; case SYSTEM_CSI2_RGB888: drvCalCfg->pixProcCfg[strmId].extract = VPS_ISS_CAL_PIX_EXRCT_B8; drvCalCfg->pixProcCfg[strmId].pack = VPS_ISS_CAL_PIX_PACK_B8; break; default: UTILS_assert((Bool) 0U); break; } if ((Bool)TRUE == drvCalCfg->isPixProcCfgValid[strmId]) { numPixProcUsed++; } } for (cmplxIoId = 0U; cmplxIoId < VPS_ISS_CAL_MAX_CMPLXIO_INST; cmplxIoId ++) { csi2Params = &pObj->createArgs.csi2Params[cmplxIoId]; drvCmplxIoCfg = &pObj->drvIssCaptureCreatePrms.cmplxIoCfg[cmplxIoId]; pObj->drvIssCaptureCreatePrms.isCmplxIoCfgValid[cmplxIoId] = csi2Params->isCmplxIoCfgValid; pObj->drvIssCaptureCreatePrms.csi2PhyClock[cmplxIoId] = csi2Params->csi2PhyClk; if ((UInt32)TRUE == csi2Params->isCmplxIoCfgValid) { drvCmplxIoCfg->enable = (UInt32)TRUE; drvCmplxIoCfg->pwrAuto = (UInt32)TRUE; drvCmplxIoCfg->clockLane.pol = csi2Params->cmplxIoCfg.clockLane.pol; drvCmplxIoCfg->clockLane.position = csi2Params->cmplxIoCfg.clockLane.position; drvCmplxIoCfg->data1Lane.pol = csi2Params->cmplxIoCfg.data1Lane.pol; drvCmplxIoCfg->data1Lane.position = csi2Params->cmplxIoCfg.data1Lane.position; drvCmplxIoCfg->data2Lane.pol = csi2Params->cmplxIoCfg.data2Lane.pol; drvCmplxIoCfg->data2Lane.position = csi2Params->cmplxIoCfg.data2Lane.position; drvCmplxIoCfg->data3Lane.pol = csi2Params->cmplxIoCfg.data3Lane.pol; drvCmplxIoCfg->data3Lane.position = csi2Params->cmplxIoCfg.data3Lane.position; drvCmplxIoCfg->data4Lane.pol = csi2Params->cmplxIoCfg.data4Lane.pol; drvCmplxIoCfg->data4Lane.position = csi2Params->cmplxIoCfg.data4Lane.position; } else { drvCmplxIoCfg->enable = (UInt32)FALSE; drvCmplxIoCfg->pwrAuto = (UInt32)FALSE; } } } ../ti_components/drivers/pdk_01_10_03_07/packages/ti/csl/soc/tda2px/hw_ctrl_core_pad.h #define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_4A_SHIFT (12U) #define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_4A_MASK (0x00001000U) #define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_4A_PADS (0U) #define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_4A_CAL (1U) #define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_3A_SHIFT (11U) #define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_3A_MASK (0x00000800U) #define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_3A_PADS (0U) #define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_3A_CAL (1U) #define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_2A_SHIFT (10U) #define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_2A_MASK (0x00000400U) #define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_2A_PADS (0U) #define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_2A_CAL (1U) #define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_1A_SHIFT (9U) #define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_1A_MASK (0x00000200U) #define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_1A_PADS (0U) #define CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_1A_CAL (1U) ../ti_components/drivers/pdk_01_10_03_07/packages/ti/drv/stw_lld/platform/src/tda2xx/platform_tda2xx.c /**************************************************************************************/ void PlatformCAL2VPortConfig(uint32_t port, uint32_t enable_mask) /* port - 1..4 for vport1A..4A, enable_mask - 1=enable 0=disable */ { switch (port) { case 1: HW_WR_FIELD32(SOC_CTRL_MODULE_CORE_CORE_PAD_REGISTERS_BASE+CTRL_CORE_CONTROL_SPARE_RW, CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_1A, enable_mask?CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_1A_CAL:CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_1A_PADS); break; case 2: HW_WR_FIELD32(SOC_CTRL_MODULE_CORE_CORE_PAD_REGISTERS_BASE+CTRL_CORE_CONTROL_SPARE_RW, CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_2A, enable_mask?CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_2A_CAL:CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_2A_PADS); break; case 3: HW_WR_FIELD32(SOC_CTRL_MODULE_CORE_CORE_PAD_REGISTERS_BASE+CTRL_CORE_CONTROL_SPARE_RW, CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_3A, enable_mask?CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_3A_CAL:CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_3A_PADS); break; case 4: HW_WR_FIELD32(SOC_CTRL_MODULE_CORE_CORE_PAD_REGISTERS_BASE+CTRL_CORE_CONTROL_SPARE_RW, CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_4A, enable_mask?CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_4A_CAL:CTRL_CORE_CONTROL_SPARE_RW_SEL_VIP_SEL_4A_PADS); break; default: break; } } config.c /**************************************************************************************/ Void ArrivalInitBaseIssCapturePrms(struct ArrivalApp *appObj) { UInt32 chan_idx=0; UInt32 port_idx=0; UInt32 csi_chan_idx=0; // UInt32 max_width=0; // UInt32 max_height=0; IssCaptureLink_CreateParams *IssCapturePrm = &appObj->graphObj.IssCaptureLinkPrm; IssCaptureLink_CreateParams_Init(IssCapturePrm); IssCapturePrm->videoIfMode = SYSTEM_VIFM_SCH_CSI2; IssCapturePrm->videoIfWidth = SYSTEM_VIFW_4LANES; IssCapturePrm->bufCaptMode = SYSTEM_CAPT_BCM_LAST_FRM_REPEAT; for (port_idx=0;port_idxcsi2Params[port_idx].isCmplxIoCfgValid = TRUE; IssCapturePrm->csi2Params[port_idx].cmplxIoCfg.clockLane.pol = FALSE; IssCapturePrm->csi2Params[port_idx].cmplxIoCfg.clockLane.position = 1; IssCapturePrm->csi2Params[port_idx].cmplxIoCfg.data1Lane.pol = FALSE; IssCapturePrm->csi2Params[port_idx].cmplxIoCfg.data1Lane.position = 2; IssCapturePrm->csi2Params[port_idx].cmplxIoCfg.data2Lane.pol = FALSE; IssCapturePrm->csi2Params[port_idx].cmplxIoCfg.data2Lane.position = 3; IssCapturePrm->csi2Params[port_idx].cmplxIoCfg.data3Lane.pol = FALSE; IssCapturePrm->csi2Params[port_idx].cmplxIoCfg.data3Lane.position = 4; IssCapturePrm->csi2Params[port_idx].cmplxIoCfg.data4Lane.pol = FALSE; IssCapturePrm->csi2Params[port_idx].cmplxIoCfg.data4Lane.position = 5; IssCapturePrm->csi2Params[port_idx].csi2PhyClk = CAPTURE_UB960_CSI2_CLOCK; if (port_idx == 1) { IssCapturePrm->csi2Params[1].cmplxIoCfg.data3Lane.position = 0; IssCapturePrm->csi2Params[1].cmplxIoCfg.data4Lane.position = 0; } } for (port_idx = 0; port_idx < ISSCAPT_LINK_MAX_CMPLXIO_INST; port_idx++) { for (chan_idx = 0; chan_idx < appObj->camPort[port_idx].remote_chan_count; chan_idx++) { struct remote_chan *remote_chan = &appObj->camPort[port_idx].remote_chan[chan_idx]; IssCaptureLink_OutParams *outParams = &IssCapturePrm->outParams[csi_chan_idx]; if (remote_chan->enable == TRUE) { outParams->width = remote_chan->inWidth; outParams->height = remote_chan->inHeight; outParams->maxWidth = remote_chan->inWidth; outParams->maxHeight = remote_chan->inHeight; outParams->dataFormat = remote_chan->inFormat; outParams->inCsi2DataFormat = remote_chan->csiFormat; outParams->inCsi2VirtualChanNum = (4*port_idx) + csi_chan_idx; outParams->numOutBuf = PIPELINE_NUM_BUF_PER_CH; outParams->outDataFormat = remote_chan->inFormat; outParams->phyInstance = appObj->camPort[port_idx].CSI_id; outParams->outBpp = GetSytemBppByCsiFormat(outParams->inCsi2DataFormat); outParams->Write2VIP = FALSE; csi_chan_idx++; if (csi_chan_idx == ISSCAPT_LINK_MAX_CH) break; } } } IssCapturePrm->outParams[0].Write2VIP = TRUE; IssCapturePrm->outParams[1].Write2VIP = TRUE; IssCapturePrm->outParams[2].Write2VIP = TRUE; IssCapturePrm->outParams[3].Write2VIP = TRUE; IssCapturePrm->outParams[4].Write2VIP = FALSE; IssCapturePrm->outParams[5].Write2VIP = FALSE; IssCapturePrm->numCh = csi_chan_idx; Vps_printf("ISS Capture config for %d channels \n", IssCapturePrm->numCh); // IssCapturePrm->callback = IssCaptureLink_CB; // IssCapturePrm->appObj = appObj; IssCapturePrm->allocBufferForRawDump = TRUE; //TODO } /**************************************************************************************/ Void InitBaseVipCapturePrms(struct mainApp *appObj) { UInt32 chan_idx=0; CaptureLink_CreateParams *pVipCapturePrm = &appObj->graphObj.VipCaptureLinkPrm; IssCaptureLink_CreateParams *IssCaptureLinkPrm = &appObj->graphObj.IssCaptureLinkPrm; IssCaptureLink_OutParams *IssChPrms = NULL; CaptureLink_VipInstParams *pInstPrm; CaptureLink_InParams *pInprms; CaptureLink_OutParams *pOutprms; CaptureLink_VipScParams *pScPrm; CaptureLink_VipPortConfig *pPortCfg; UInt32 portId[10]; portId[0] = SYSTEM_CAPTURE_INST_VIP1_SLICE1_PORTA; portId[1] = SYSTEM_CAPTURE_INST_VIP1_SLICE2_PORTA; portId[2] = SYSTEM_CAPTURE_INST_VIP2_SLICE1_PORTA; portId[3] = SYSTEM_CAPTURE_INST_VIP2_SLICE2_PORTA; CaptureLink_CreateParams_Init(pVipCapturePrm); pVipCapturePrm->numVipInst = 4; pVipCapturePrm->numDssWbInst = 0; UTILS_assert(pVipCapturePrm->numVipInst<=SYSTEM_CAPTURE_VIP_INST_MAX); UTILS_assert(pVipCapturePrm->numDssWbInst<=SYSTEM_CAPTURE_DSSWB_INST_MAX); for (chan_idx=0; chan_idxnumVipInst; chan_idx++) { pInstPrm = &pVipCapturePrm->vipInst[chan_idx]; IssChPrms = &IssCaptureLinkPrm->outParams[chan_idx]; (void)IssChPrms; pInstPrm->vipInstId = portId[chan_idx]; pInstPrm->videoIfMode = SYSTEM_VIFM_SCH_DS_HSYNC_VSYNC; pInstPrm->videoIfWidth = SYSTEM_VIFW_8BIT; pInstPrm->bufCaptMode = SYSTEM_CAPT_BCM_LAST_FRM_REPEAT;//SYSTEM_CAPT_BCM_FRM_DROP;//SYSTEM_CAPT_BCM_LAST_FRM_REPEAT; pInstPrm->numStream = 1; pInprms = &pInstPrm->inParams; pInprms->width = 1920;//IssChPrms->width; pInprms->height = 1080;//IssChPrms->height; pInprms->dataFormat = SYSTEM_DF_YUV422P; ////FIXME TODO pInprms->scanFormat = SYSTEM_SF_PROGRESSIVE; pOutprms = &pInstPrm->outParams[0]; pOutprms->width = pInprms->width; pOutprms->height = pInprms->height; pOutprms->dataFormat = SYSTEM_DF_YUV420SP_UV; pOutprms->maxWidth = pOutprms->width; pOutprms->maxHeight = pOutprms->height; pOutprms->scEnable = FALSE; /* sub-frame not supported, set to FALSE */ pOutprms->subFrmPrms.subFrameEnable = FALSE; pOutprms->subFrmPrms.numLinesPerSubFrame = 0; pOutprms->frameSkipMask = 0; pScPrm = &pInstPrm->scPrms; pScPrm->inCropCfg.cropStartX = 0; pScPrm->inCropCfg.cropStartY = 0; pScPrm->inCropCfg.cropWidth = pInprms->width; pScPrm->inCropCfg.cropHeight = pInprms->height; pScPrm->scCfg.bypass = FALSE; pScPrm->scCfg.nonLinear = FALSE; pScPrm->scCfg.stripSize = 0; pScPrm->userCoeff = FALSE; pPortCfg = &pInstPrm->vipPortCfg; pPortCfg->syncType = SYSTEM_VIP_SYNC_TYPE_DIS_SINGLE_YUV; pPortCfg->intfCfg.clipActive = FALSE; pPortCfg->intfCfg.clipBlank = FALSE; pPortCfg->intfCfg.intfWidth = SYSTEM_VIFW_16BIT; pPortCfg->disCfg.fidSkewPostCnt = 0; pPortCfg->disCfg.fidSkewPreCnt = 0; pPortCfg->disCfg.lineCaptureStyle = SYSTEM_VIP_LINE_CAPTURE_STYLE_HSYNC; pPortCfg->disCfg.fidDetectMode = SYSTEM_VIP_FID_DETECT_MODE_VSYNC; pPortCfg->disCfg.actvidPol = SYSTEM_POL_HIGH; pPortCfg->disCfg.vsyncPol = SYSTEM_POL_HIGH; pPortCfg->disCfg.hsyncPol = SYSTEM_POL_HIGH; pPortCfg->disCfg.discreteBasicMode = FALSE; pPortCfg->comCfg.ctrlChanSel = SYSTEM_VIP_CTRL_CHAN_SEL_7_0; pPortCfg->comCfg.ancChSel8b = SYSTEM_VIP_ANC_CH_SEL_8B_LUMA_SIDE; pPortCfg->comCfg.pixClkEdgePol = SYSTEM_EDGE_POL_RISING; pPortCfg->comCfg.invertFidPol = FALSE; pPortCfg->comCfg.enablePort = FALSE; pPortCfg->comCfg.expectedNumLines = pInprms->height; pPortCfg->comCfg.expectedNumPix = pInprms->width; pPortCfg->comCfg.repackerMode = SYSTEM_VIP_REPACK_CBA_TO_CBA; pPortCfg->actCropEnable = FALSE; pPortCfg->actCropCfg.srcNum = 0; pPortCfg->actCropCfg.cropCfg.cropStartX = 0; pPortCfg->actCropCfg.cropCfg.cropStartY = 0; pPortCfg->actCropCfg.cropCfg.cropWidth = pInprms->width; pPortCfg->actCropCfg.cropCfg.cropHeight = pInprms->height; pPortCfg->ancCropEnable = FALSE; pPortCfg->ancCropCfg.srcNum = 0; pPortCfg->ancCropCfg.cropCfg.cropStartX = 0; pPortCfg->ancCropCfg.cropCfg.cropStartY = 0; pPortCfg->ancCropCfg.cropCfg.cropWidth = pInprms->width; pPortCfg->ancCropCfg.cropCfg.cropHeight = pInprms->height; pInstPrm->numBufs = CAPTURE_LINK_NUM_BUFS_PER_CH_DEFAULT; } } pipeline.c create(...) { status = System_linkCreate(pObj->IssCaptureLinkID, &pObj->IssCaptureLinkPrm, sizeof(IssCaptureLink_CreateParams)); UTILS_assert(status == SYSTEM_LINK_STATUS_SOK); PlatformUnlockMMR(); PlatformCAL2VPortConfig(1, TRUE); PlatformCAL2VPortConfig(2, TRUE); PlatformCAL2VPortConfig(3, TRUE); PlatformCAL2VPortConfig(4, TRUE); PlatformLockMMR(); pObj->VipCaptureLinkPrm.callback = &CaptureLink_CB; pObj->VipCaptureLinkPrm.appObj = appObj; status = System_linkCreate(pObj->VipCaptureLinkID, &pObj->VipCaptureLinkPrm, sizeof(CaptureLink_CreateParams)); UTILS_assert(status == SYSTEM_LINK_STATUS_SOK); } start(..) { status = System_linkStart(pObj->VipCaptureLinkID); UTILS_assert(status == SYSTEM_LINK_STATUS_SOK); status = System_linkStart(pObj->IssCaptureLinkID); UTILS_assert(status == SYSTEM_LINK_STATUS_SOK); }