DDR2 -> DDR3

h3. Comparing Before

0x44e00040 0x00030000 -> 0x00000002
CM_PER_ELM_CLKCTRL

MODULEMODE Disabled to Enable
IDLEST Disable to Functional

0x44e0042c 0x00011317 -> 0x00001901
CM_CLKSEL_DPLL_MPU

DPLL_DIV divider from 22 to 1
DPLL_MULT multiplier from 275 to 25


0x44e00440 0x00010a17 -> 0x00019017
CM_CLKSEL_DPLL_DDR

DPLL_MULT multiplier from 266 to 400

h3. Comparing standby

Same as Before

h3. Comparing after resume

0x44e00000 0x18024d02 -> 0x00000102
CM_PER_L4LS_CLKSTCTRL

CLKACTIVITY_UART_GFCLK Act -> Inact
CLKACTIVITY_CAN_CLK Act -> Inact
CLKACTIVITY_TIMER2_CLK Act -> Inact
CLKACTIVITY_LCDC_GCLK Act -> Inact
CLKACTIVITY_TIMER5_GCLK Act -> Inact
CLKACTIVITY_TIMER6_GCLK Act -> Inact


0x44e0000c 0x000000d6 -> 0x00000016
CM_PER_L3_CLKSTCTRL

CLKACTIVITY_CPTS_RFT_GCLK Act -> Inact
CLKACTIVITY_MCASP_GCLK Act -> Inact


0x44e00014 0x00000002 -> 0x00070000
CM_PER_CPGMAC0_CLKCTRL
0x44e00018 0x00000002 -> 0x00070000
CM_PER_LCDC_CLKCTRL
0x44e00024 0x00000002 -> 0x00070000
CM_PER_TPTC0_CLKCTRL
0x44e000fc 0x00000002 -> 0x00030000
CM_PER_TPTC1_CLKCTRL
0x44e00100 0x00000002 -> 0x00030000
CM_PER_TPTC2_CLKCTRL

MODULEMODE Enable -> Disabled
IDLEST Func -> Disable
STBYST Func -> Standby


0x44e00038 0x00000002 -> 0x00030000
CM_PER_UART5_CLKCTRL
0x44e00068 0x00000002 -> 0x00030000
CM_PER_MCASP1_CLKCTRL
0x44e0006c 0x00000002 -> 0x00030000
CM_PER_UART1_CLKCTRL
0x44e00070 0x00000002 -> 0x00030000
CM_PER_UART2_CLKCTRL
0x44e00074 0x00000002 -> 0x00030000
CM_PER_UART3_CLKCTRL
0x44e00078 0x00000002 -> 0x00030000
CM_PER_UART4_CLKCTRL
0x44e00080 0x00000002 -> 0x00030000
CM_PER_TIMER2_CLKCTRL
0x44e000bc 0x00000002 -> 0x00030000
CM_PER_TPCC_CLKCTRL
0x44e000c0 0x00000002 -> 0x00030000
CM_PER_DCAN0_CLKCTRL
0x44e000c4 0x00000002 -> 0x00030000
CM_PER_DCAN1_CLKCTRL
0x44e000ec 0x00000002 -> 0x00030000
CM_PER_TIMER5_CLKCTRL
0x44e000f0 0x00000002 -> 0x00030000
CM_PER_TIMER6_CLKCTRL
0x44e00110 0x00000002 -> 0x00030000
CM_PER_MAILBOX0_CLKCTRL

MODULEMODE Enable -> Disabled
IDLEST Func -> Disable


0x44e0011c 0x0000007a -> 0x0000000a
CM_PER_L4HS_CLKSTCTRL

CLKACTIVITY_CPSW_250MHZ_GCLK  Act -> Inact
CLKACTIVITY_CPSW_50MHZ_GCLK Act -> Inact
CLKACTIVITY_CPSW_5MHZ_GCLK Act -> Inact


0x44e00144 0x00000012 -> 0x00000001
CM_PER_CPSW_CLKSTCTRL

CLKTRCTRL SW_WKUP -> SW_SLEEP
CLKACTIVITY_CPSW_125MHz_GCLK Act -> Inact

0x44e00148 0x00000012 -> 0x00000001
CM_PER_LCDC_CLKSTCTRL

CLKTRCTRL SW_WKUP -> SW_SLEEP
CLKACTIVITY_LCDC_L3_OCP_GCLK Act -> Inact


0x44e0042c 0x00011317 -> 0x00001901
CM_CLKSEL_DPLL_MPU
0x44e00440 0x00010a17 -> 0x00019017
CM_CLKSEL_DPLL_DDR

Same


0x44e00484 0x00000228 -> 0x00000028
CM_DIV_M5_DPLL_CORE

ST_HSDIVIDER_CLKOUT2 gated -> enabled


0x44e004a4 0x00000201 -> 0x00000001
CM_DIV_M2_DPLL_DISP

ST_DPLL_CLKOUT 	enabled -> gated


0x44e00604 0x00040002 -> 0x00000002
CM_MPU_MPU_CLKCTRL

STBYST Standby -> Func


0x44e00900 0x00000002 -> 0x00000001
CM_GFX_L3_CLKSTCTRL
0x44e0090c 0x00000002 -> 0x00000001
CM_GFX_L4LS_GFX_CLKSTCTRL

CLKTRCTRL SW_WKUP -> SW_SLEEP


0x44e01110 0x00000037 -> 0x00000000
PM_GFX_PWRSTST

PowerStateSt ON -> OFF
LogicStateSt ON -> OFF
GFX_MEM_StateSt Mem_on -> Mem_off