ddr3B_levling_1


C66xx_0: GEL Output: ****************************************************************************************************************
C66xx_0: GEL Output: ***************** DDR3B Leveling Errors *********************
C66xx_0: GEL Output:  PGSR0[27]:	WEERR has 	** No Error **
C66xx_0: GEL Output:  PGSR0[26]:	REERR has 	** No Error **
C66xx_0: GEL Output:  PGSR0[25]:	WDERR has 	** No Error **
C66xx_0: GEL Output:  PGSR0[24]:	RDERR has 	** Error **
C66xx_0: GEL Output:  PGSR0[23]:	WLAERR has 	** Error **
C66xx_0: GEL Output:  PGSR0[22]:	QSGERR has 	** Error **
C66xx_0: GEL Output:  PGSR0[21]:	WLERR has 	** Error **
C66xx_0: GEL Output:  PGSR0[20]:	ZCERR has 	** Error **

C66xx_0: GEL Output:  PGSR0[11]:	WEDONE is 	** Not Set **
C66xx_0: GEL Output:  PGSR0[10]:	REDONE is 	** Not Set **
C66xx_0: GEL Output:  PGSR0[9]:		WDDONE is 	** Not Set **
C66xx_0: GEL Output:  PGSR0[8]:		RDDONE is 	** Set **
C66xx_0: GEL Output:  PGSR0[7]:		WLADONE is 	** Set **
C66xx_0: GEL Output:  PGSR0[6]:		QSGDONE is 	** Set **
C66xx_0: GEL Output:  PGSR0[5]:		WLDONE is 	** Set **
C66xx_0: GEL Output:  PGSR0[4]:		DIDONE is 	** Set **
C66xx_0: GEL Output:  PGSR0[3]:		ZCDONE is 	** Set **
C66xx_0: GEL Output:  PGSR0[2]:		DCDONE is 	** Set **
C66xx_0: GEL Output:  PGSR0[1]:		PLDONE is 	** Set **
C66xx_0: GEL Output:  PGSR0[0]:		IDONE is 	** Set **

C66xx_0: GEL Output: ********************************************************
C66xx_0: GEL Output: Leveling Errors by Byte Lane:

C66xx_0: GEL Output: Byte Lane 0:
C66xx_0: GEL Output: 	DX0GSR2[6]:   WEERR has 		** No Error **
C66xx_0: GEL Output: 	DX0GSR2[4]:   REERR has 		** No Error **
C66xx_0: GEL Output: 	DX0GSR2[2]:   WDERR has 		** No Error **
C66xx_0: GEL Output: 	DX0GSR2[0]:   RDERR has 		** Error **
C66xx_0: GEL Output: 	DX0GSR0[25]:   QSGERR on Rank1 has 	** No Error **
C66xx_0: GEL Output: 	DX0GSR0[24]:   QSGERR on Rank0 has 	** Error **
C66xx_0: GEL Output: 	DX0GSR0[6]:    WLERR has 		** Error **
C66xx_0: GEL Output: Byte Lane 1:
C66xx_0: GEL Output: 	DX1GSR2[6]:   WEERR has 		** No Error **
C66xx_0: GEL Output: 	DX1GSR2[4]:   REERR has 		** No Error **
C66xx_0: GEL Output: 	DX1GSR2[2]:   WDERR has 		** No Error **
C66xx_0: GEL Output: 	DX1GSR2[0]:   RDERR has 		** Error **
C66xx_0: GEL Output: 	DX1GSR0[25]:   QSGERR on Rank1 has 	** No Error **
C66xx_0: GEL Output: 	DX1GSR0[24]:   QSGERR on Rank0 has 	** Error **
C66xx_0: GEL Output: 	DX1GSR0[6]:    WLERR has 		** Error **
C66xx_0: GEL Output: Byte Lane 2:
C66xx_0: GEL Output: 	DX2GSR2[6]:   WEERR has 		** No Error **
C66xx_0: GEL Output: 	DX2GSR2[4]:   REERR has 		** No Error **
C66xx_0: GEL Output: 	DX2GSR2[2]:   WDERR has 		** No Error **
C66xx_0: GEL Output: 	DX2GSR2[0]:   RDERR has 		** Error **
C66xx_0: GEL Output: 	DX2GSR0[25]:   QSGERR on Rank1 has 	** No Error **
C66xx_0: GEL Output: 	DX2GSR0[24]:   QSGERR on Rank0 has 	** Error **
C66xx_0: GEL Output: 	DX2GSR0[6]:    WLERR has 		** Error **
C66xx_0: GEL Output: Byte Lane 3:
C66xx_0: GEL Output: 	DX3GSR2[6]:   WEERR has 		** No Error **
C66xx_0: GEL Output: 	DX3GSR2[4]:   REERR has 		** No Error **
C66xx_0: GEL Output: 	DX3GSR2[2]:   WDERR has 		** No Error **
C66xx_0: GEL Output: 	DX3GSR2[0]:   RDERR has 		** Error **
C66xx_0: GEL Output: 	DX3GSR0[25]:   QSGERR on Rank1 has 	** No Error **
C66xx_0: GEL Output: 	DX3GSR0[24]:   QSGERR on Rank0 has 	** Error **
C66xx_0: GEL Output: 	DX3GSR0[6]:    WLERR has 		** Error **
C66xx_0: GEL Output: Byte Lane 4:
C66xx_0: GEL Output: 	DX4GSR2[6]:   WEERR has 		** No Error **
C66xx_0: GEL Output: 	DX4GSR2[4]:   REERR has 		** No Error **
C66xx_0: GEL Output: 	DX4GSR2[2]:   WDERR has 		** No Error **
C66xx_0: GEL Output: 	DX4GSR2[0]:   RDERR has 		** Error **
C66xx_0: GEL Output: 	DX4GSR0[25]:   QSGERR on Rank1 has 	** No Error **
C66xx_0: GEL Output: 	DX4GSR0[24]:   QSGERR on Rank0 has 	** Error **
C66xx_0: GEL Output: 	DX4GSR0[6]:    WLERR has 		** Error **
C66xx_0: GEL Output: Byte Lane 5:
C66xx_0: GEL Output: 	DX5GSR2[6]:   WEERR has 		** No Error **
C66xx_0: GEL Output: 	DX5GSR2[4]:   REERR has 		** No Error **
C66xx_0: GEL Output: 	DX5GSR2[2]:   WDERR has 		** No Error **
C66xx_0: GEL Output: 	DX5GSR2[0]:   RDERR has 		** Error **
C66xx_0: GEL Output: 	DX5GSR0[25]:   QSGERR on Rank1 has 	** No Error **
C66xx_0: GEL Output: 	DX5GSR0[24]:   QSGERR on Rank0 has 	** Error **
C66xx_0: GEL Output: 	DX5GSR0[6]:    WLERR has 		** Error **
C66xx_0: GEL Output: Byte Lane 6:
C66xx_0: GEL Output: 	DX6GSR2[6]:   WEERR has 		** No Error **
C66xx_0: GEL Output: 	DX6GSR2[4]:   REERR has 		** No Error **
C66xx_0: GEL Output: 	DX6GSR2[2]:   WDERR has 		** No Error **
C66xx_0: GEL Output: 	DX6GSR2[0]:   RDERR has 		** Error **
C66xx_0: GEL Output: 	DX6GSR0[25]:   QSGERR on Rank1 has 	** No Error **
C66xx_0: GEL Output: 	DX6GSR0[24]:   QSGERR on Rank0 has 	** Error **
C66xx_0: GEL Output: 	DX6GSR0[6]:    WLERR has 		** Error **
C66xx_0: GEL Output: Byte Lane 7:
C66xx_0: GEL Output: 	DX7GSR2[6]:   WEERR has 		** No Error **
C66xx_0: GEL Output: 	DX7GSR2[4]:   REERR has 		** No Error **
C66xx_0: GEL Output: 	DX7GSR2[2]:   WDERR has 		** No Error **
C66xx_0: GEL Output: 	DX7GSR2[0]:   RDERR has 		** Error **
C66xx_0: GEL Output: 	DX7GSR0[25]:   QSGERR on Rank1 has 	** No Error **
C66xx_0: GEL Output: 	DX7GSR0[24]:   QSGERR on Rank0 has 	** Error **
C66xx_0: GEL Output: 	DX7GSR0[6]:    WLERR has 		** Error **
C66xx_0: GEL Output: Byte Lane 8:
C66xx_0: GEL Output: 	DX8GSR2[6]:   WEERR has 		** No Error **
C66xx_0: GEL Output: 	DX8GSR2[4]:   REERR has 		** No Error **
C66xx_0: GEL Output: 	DX8GSR2[2]:   WDERR has 		** No Error **
C66xx_0: GEL Output: 	DX8GSR2[0]:   RDERR has 		** Error **
C66xx_0: GEL Output: 	DX8GSR0[25]:   QSGERR on Rank1 has 	** No Error **
C66xx_0: GEL Output: 	DX8GSR0[24]:   QSGERR on Rank0 has 	** Error **
C66xx_0: GEL Output: 	DX8GSR0[6]:    WLERR has 		** Error **
C66xx_0: GEL Output: ****************************************************************************************************************