// SPDX-License-Identifier: GPL-2.0 /* * vision-apps: device-tree overlay * * Copyright (C) 2019 - 2021 Texas Instruments Incorporated - http://www.ti.com/ */ #include "invo-k3-j721e-rtos-memory-map.dtsi" #include "devicetree.dtsi" #include #include #include #include "k3-pinctrl.h" #include &{/} { aliases { ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3"; //ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4"; }; #if 0 gpio_rst { #gpio-cells = <2>; compatible = "phy-rst-gpio"; pinctrl-names = "default"; pinctrl-0 = <&mygpio0_pins_default>; rst-gpio = <&main_gpio0 2 GPIO_ACTIVE_LOW>, <&main_gpio0 7 GPIO_ACTIVE_LOW>, <&main_gpio0 10 GPIO_ACTIVE_LOW>; status = "okay"; }; #endif }; &cmn_refclk1 { status = "okay"; clock-frequency = <100000000>; }; &cpsw0 { status = "okay"; }; &cpsw0_port1 { status = "okay"; phy-handle = <&cpsw9g_phy0>; phy-mode = "sgmii"; mac-address = [00 00 00 00 00 00]; phys = <&cpsw0_phy_gmii_sel 1>, <&serdes0_qsgmii_link>; phy-names = "mac", "serdes"; }; &cpsw0_port2 { status = "okay"; phy-handle = <&cpsw9g_phy1>; phy-mode = "sgmii"; mac-address = [00 00 00 00 00 00]; phys = <&cpsw0_phy_gmii_sel 2>; phy-names = "mac"; }; &cpsw0_port3 { status = "okay"; phy-handle = <&cpsw9g_phy2>; phy-mode = "sgmii"; mac-address = [00 00 00 00 00 00]; phys = <&cpsw0_phy_gmii_sel 3>, <&serdes1_qsgmii_link>; phy-names = "mac","serdes"; }; &cpsw9g_mdio { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mymdio1_pins_default>; // reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>; reset-gpios = <&main_gpio0 7 GPIO_ACTIVE_LOW>, <&main_gpio0 10 GPIO_ACTIVE_LOW>, <&main_gpio0 2 GPIO_ACTIVE_LOW>; // reset-delay-us = <20>; reset-post-delay-us = <120000>; #address-cells = <1>; #size-cells = <0>; cpsw9g_phy0: ethernet-phy@2 { compatible = "rtk,rtl9010","ethernet-phy-ieee802.3-c22"; reg = <2>; // ethphy-mode = "master"; // ethphy-speed = <1000>; //reset-gpios = <&main_gpio0 2 GPIO_ACTIVE_LOW>; // ti,rx-internal-delay = ; // ti,fifo-depth = ; // ti,min-output-impedance; }; cpsw9g_phy1: ethernet-phy@3 { compatible = "rtk,rtl9010","ethernet-phy-ieee802.3-c22"; reg = <3>; // ethphy-mode = "master"; // ethphy-speed = <1000>; //reset-gpios = <&main_gpio0 7 GPIO_ACTIVE_LOW>; // ti,rx-internal-delay = ; // ti,fifo-depth = ; // ti,min-output-impedance; }; cpsw9g_phy2: ethernet-phy@1 { // compatible = "rtk,rtl9010","ethernet-phy-ieee802.3-c22"; reg = <1>; // ethphy-mode = "master"; // ethphy-speed = <1000>; //reset-gpios = <&main_gpio0 10 GPIO_ACTIVE_LOW>; // ti,rx-internal-delay = ; // ti,fifo-depth = ; // ti,min-output-impedance; }; }; &serdes_ln_ctrl { idle-states = , , , , , , , , , , , ; }; // &cmn_refclk { // status = "okay"; // clock-frequency = <100000000>; // }; &wiz0_pll1_refclk { assigned-clocks = <&wiz0_pll1_refclk>; assigned-clock-parents = <&cmn_refclk1>; }; &wiz0_refclk_dig { assigned-clocks = <&wiz0_refclk_dig>; assigned-clock-parents = <&cmn_refclk1>; }; &wiz1_pll1_refclk { assigned-clocks = <&wiz1_pll1_refclk>; assigned-clock-parents = <&cmn_refclk1>; }; &wiz1_refclk_dig { assigned-clocks = <&wiz1_refclk_dig>; assigned-clock-parents = <&cmn_refclk1>; }; &serdes_wiz0 { status = "okay"; }; &serdes_wiz1 { status = "okay"; }; &serdes0 { status = "okay"; assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>; assigned-clock-parents = <&wiz0_pll0_refclk>; #address-cells = <1>; #size-cells = <0>; serdes0_qsgmii_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>; cdns,phy-type = ; resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; }; }; &serdes1 { status = "okay"; assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>; assigned-clock-parents = <&wiz1_pll0_refclk>; // assigned-clock-parents = <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>; #address-cells = <1>; #size-cells = <0>; serdes1_qsgmii_link: phy@1 { reg = <0>; cdns,num-lanes = <1>; #phy-cells = <0>; cdns,phy-type = ; resets = <&serdes_wiz1 1>; }; }; #if 0 &main_r5fss0_core0_shared_memory_queue_region { status = "disabled"; }; &main_r5fss0_core0_shared_memory_bufpool_region { status = "disabled"; }; #endif &serdes_wiz2 { status = "disabled"; }; &serdes_wiz3 { status = "disabled"; }; &serdes_wiz4 { status = "disabled"; }; &serdes2 { status = "disabled"; }; &serdes3 { status = "disabled"; }; &mhdp { status = "disabled"; }; &dss { status = "disabled"; }; &ti_csi2rx0 { status = "disabled"; }; &ti_csi2rx1 { status = "disabled"; }; #if 0 &d5520 { status = "disabled"; }; &vxe384 { status = "disabled"; }; #endif /* new add */ &pcie0_rc { status = "disabled"; }; &pcie1_rc { status = "disabled"; }; &pcie2_rc { status = "disabled"; }; &main_uart1 { status = "disabled"; }; &main_uart4 { status = "disabled"; }; &main_uart6 { status = "disabled"; }; &pru0_0{ status = "disabled"; }; &rtu0_0{ status = "disabled"; }; &tx_pru0_0{ status = "disabled"; }; &pru0_1{ status = "disabled"; }; &rtu0_1{ status = "disabled"; }; &tx_pru0_1{ status = "disabled"; }; &pru1_0{ status = "disabled"; }; &rtu1_0{ status = "disabled"; }; &tx_pru1_0{ status = "disabled"; }; &pru1_1{ status = "disabled"; }; &rtu1_1{ status = "disabled"; }; &tx_pru1_1{ status = "disabled"; }; &ufs_wrapper{ status = "disabled"; }; &pcm3168a_1{ status = "disabled"; }; &sound0{ status = "disabled"; }; &mcasp10{ status = "disabled"; }; &main_i2c0{ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&myi2c0_pins_default>; }; &main_i2c1{ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&myi2c1_pins_default &mygpio0_pins_default &mygpio1_pins_default &myvout0_pins_default &mywkup_gpio1_pins_default>; }; &main_i2c2{ status = "disabled"; }; &main_i2c3{ status = "disabled"; }; &main_i2c4{ status = "disabled"; }; &main_i2c5{ status = "disabled"; }; &main_i2c6{ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&myi2c6_pins_default>; }; #if 0 &main_sdhci1 { status = "disabled"; }; #endif &main_crypto { status = "disabled"; }; &usbss1 { status = "disabled"; }; &main_mcan0 { status = "disabled"; }; &main_mcan1 { status = "disabled"; }; &main_mcan2 { status = "disabled"; }; /* disable mcu modules*/ &mcu_uart0 { /* MCU UART is used by MCU apps */ status = "disabled"; }; &mcu_i2c1{ status = "disabled"; }; &mcu_mcan0 { status = "disabled"; }; &mcu_mcan1 { status = "disabled"; }; &ospi1 { status = "disabled"; }; &tscadc0 { status = "disabled"; }; &tscadc1 { status = "disabled"; }; &dphy0 { status = "disabled"; }; &dphy1 { status = "disabled"; }; &transceiver1 { status = "disabled"; }; &transceiver2 { status = "disabled"; }; &transceiver3 { status = "disabled"; }; &transceiver4 { status = "disabled"; }; &gpio_keys { status = "disabled"; }; #if 1 &mcu_cpsw { status = "disabled"; }; #endif //mcu r5fss0 &mcu_r5fss0 { status = "disabled"; }; //main r5fss1 &main_r5fss1 { status = "disabled"; }; #if 0 //mcu0_1 &vision_apps_mcu_r5fss0_core1_dma_memory_region { status = "disabled"; }; &vision_apps_mcu_r5fss0_core1_memory_region { status = "disabled"; }; //main1_0 and main1_1 &vision_apps_main_r5fss1_core0_dma_memory_region { status = "disabled"; }; &vision_apps_main_r5fss1_core0_memory_region { status = "disabled"; }; &vision_apps_main_r5fss1_core1_dma_memory_region { status = "disabled"; }; &vision_apps_main_r5fss1_core1_memory_region { status = "disabled"; }; &mailbox0_cluster2 { status = "disabled"; }; &main_r5fss1 { status = "disabled"; }; //main c66_0 and main c66_1 &c66_0 { status = "disabled"; }; &c66_1 { status = "disabled"; }; &mailbox0_cluster3 { status = "disabled"; }; &vision_apps_c66_0_dma_memory_region { status = "disabled"; }; &vision_apps_c66_0_memory_region { status = "disabled"; }; &vision_apps_c66_1_dma_memory_region { status = "disabled"; }; &vision_apps_c66_1_memory_region { status = "disabled"; }; //main c71 &c71_0 { status = "disabled"; }; &mailbox0_cluster4 { status = "disabled"; }; &vision_apps_c71_0_dma_memory_region { status = "disabled"; }; &vision_apps_c71_0_memory_region { status = "disabled"; }; #endif &main_spi0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&myspi0_pins_default>; dmas = <&main_udmap 0xc600>, <&main_udmap 0x4600>; dma-names = "tx0", "rx0"; /*default: ti,pindir-d0-in-d1-out */ ti,pindir-d0-out-d1-in; spidev@0{ compatible = "rohm,dh2228fv"; reg = <0>;//0-spidev1.0,3-spidev1.3 spi-max-frequency = <24000000>; spi-cpol = <0>; //1-89501,0-89541 spi-cpha = <0>; //1-89501,0-89541 }; }; &main_spi1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&myspi1_pins_default>; dmas = <&main_udmap 0xc604>, <&main_udmap 0x4604>; dma-names = "tx0", "rx0"; /*default: ti,pindir-d0-in-d1-out */ ti,pindir-d0-out-d1-in; spidev@0{ compatible = "rohm,dh2228fv"; reg = <0>;//0-spidev1.0,3-spidev1.3 spi-max-frequency = <24000000>; spi-cpol = <0>; //1-89501,0-89541 spi-cpha = <0>; //1-89501,0-89541 }; }; &main_spi2 { status="disabled"; }; &main_spi3 { status="disabled"; }; &main_spi5 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&myspi5_pins_default>; dmas = <&main_udmap 0xc61c>, <&main_udmap 0x461c>; dma-names = "tx0", "rx0"; /*default: ti,pindir-d0-in-d1-out */ ti,pindir-d0-out-d1-in; spidev@0{ compatible = "rohm,dh2228fv"; reg = <0>;//0-spidev1.0,3-spidev1.3 spi-max-frequency = <24000000>; spi-cpol = <0>; //1-89501,0-89541 spi-cpha = <0>; //1-89501,0-89541 }; }; #if 0 &main_spi5 { status = "okay"; spi-slave; pinctrl-names = "default"; pinctrl-0 = <&myspi5_pins_default>; /*default: ti,pindir-d0-in-d1-out */ /*ti,pindir-d0-out-d1-in; */ slave@0{ compatible = "rohm,dh2228fv"; reg = <0>;//0-spidev1.0,3-spidev1.3 spi-max-frequency = <24000000>; spi-cpol = <0>; //1-89501,0-89541 spi-cpha = <0>; //1-89501,0-89541 }; }; #endif &main_spi6 { status="disabled"; }; /* * MCSPI4 is directly connected as a slave to MCU_MCSPI2 by default at power-up. MCSPI4 and * MCU_MCSPI2 are not pinned out externally. */ &mcu_spi2 { status="disabled"; spidev@0 { compatible = "rohm,dh2228fv"; reg = <0>; spi-max-frequency = <24000000>; }; };