// SPDX-License-Identifier: GPL-2.0
/**
 * DT Overlay for CPSW9G in RGMII mode using J7 GESI EXP BRD board with
 * J721E board.
 *
 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/pinctrl/k3.h>

/ {
	fragment@102 {
		target-path = "/";
		__overlay__ {
			aliases {
				ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
				ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
				ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
				ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
                ethernet5 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5";
				ethernet6 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6";
				ethernet7 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7";
				ethernet8 = "/bus@100000/ethernet@c000000/ethernet-ports/port@8";
			};
		};
	};
};

&cpsw0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins_default
		     &rgmii5_pins_default>;
};

&cpsw0_port1 {
	status = "disabled";
};

&cpsw0_port8 {
	status = "disabled";
};

&cpsw0_port3 {
	status = "disabled";
};

&cpsw0_port4 {
	status = "disabled";
};

&cpsw0_port2 {
	status = "disabled";
};

&cpsw0_port5 {
	status = "okay";
	phy-handle = <&cpsw9g_phy5>;
	phy-mode = "rgmii-rxid";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 5>;
};


&cpsw0_port6 {
	status = "disabled";
};

&cpsw0_port7 {
	status = "disabled";
};

&cpsw0_port8 {
	status = "disabled";
};

&cpsw9g_mdio {
	bus_freq = <1000000>;
	#address-cells = <1>;
	#size-cells = <0>;

	cpsw9g_phy5: ethernet-phy@5 {
		reg = <5>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		ti,min-output-impedance;
	};
};

&cpsw9g_virt_mac {
	status = "disabled";
};

&exp1 {
	p15-hog {
		/* P15 - EXP_MUX2 */
		gpio-hog;
		gpios = <13 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "EXP_MUX2";
	};

	p16-hog {
		/* P16 - EXP_MUX3 */
		gpio-hog;
		gpios = <14 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "EXP_MUX3";
	};
};

&exp2 {
	qsgmii-line-hog {
		gpio-hog;
		gpios = <16 GPIO_ACTIVE_HIGH>;
		output-low;
		line-name = "qsgmii-pwrdn-line";
	};
};

&main_pmx0 {
	mdio_pins_default: mdio-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */
			J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */
		>;
	};

	rgmii5_pins_default: rgmii5-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x184, PIN_INPUT, 0) /* (T23) RGMII5_RD0 */
			J721E_IOPAD(0x180, PIN_INPUT, 0) /* (R23) RGMII5_RD1 */
			J721E_IOPAD(0x17c, PIN_INPUT, 0) /* (U24) RGMII5_RD2 */
			J721E_IOPAD(0x178, PIN_INPUT, 0) /* (U27) RGMII5_RD3 */
			J721E_IOPAD(0x174, PIN_INPUT, 0) /* (U25) RGMII5_RXC */
			J721E_IOPAD(0x15c, PIN_INPUT, 0) /* (U26) RGMII5_RX_CTL */
			J721E_IOPAD(0x16c, PIN_OUTPUT, 0) /* (U28) RGMII5_TD0 */
			J721E_IOPAD(0x168, PIN_OUTPUT, 0) /* (V27) RGMII5_TD1 */
			J721E_IOPAD(0x164, PIN_OUTPUT, 0) /* (V29) RGMII5_TD2 */
			J721E_IOPAD(0x160, PIN_OUTPUT, 0) /* (V28) RGMII5_TD3 */
			J721E_IOPAD(0x170, PIN_OUTPUT, 0) /* (U29) RGMII5_TXC */
			J721E_IOPAD(0x158, PIN_OUTPUT, 0) /* (U23) RGMII5_TX_CTL */
		>;
	};

};

&main_r5fss0_core0 {
	firmware-name = "pdk-ipc/ipc_echo_test_mcu2_0_release_strip.xer5f";
};