#!/bin/sh

# timer_run.sh
#
# This script configures Timer4 to be run
# on the VP1 Board. After configured,
# the timer runs indefinitely at a fixed
# freq and duty cycle, fed from the
# internal CLK_M_OSC clock
#

echo "Configuring Timer 6...\n"
#configurations changed for Timer6
# Enable Timer4's clock in CM_PER
# This allows us to access it's control regs
#devmem2 0x44e00088 w 0x2

# Set the Pinmux for Timer4 (0x2 because its mode 2 of this pin)
# Using the pin mux linux driver from the SDK
# echo 0x22 > /sys/kernel/debug/omap_mux/xdma_event_intr0

#Select TIMER6 CLOCK SOURCE
devmem2 0x44e0051c w 0x1
#Enable timer to access its ctrl regs
devmem2 0x44e000f0 w 0x2

# Timer configurations.. Stop Timer.
# Auto-Reload
# Compare Mode Enabled
# Trigger set on overflow
# Toggle Mode
#devmem2 0x48044038 w 0x1842
devmem2 0x48048038 w 0x68

# Write to the CM_DPLL registers to select the clk source
# Selected the clk source for the Timer4
# This should be &= (default 0x12) (writing a 0x2 for 32kHz)
#0x1 = SEL2 : Select CLK_M_OSC clock
#devmem2 0x44e00510 w 0x1
#devmem2 0x44e0051c w 0x1
# Initial count value
#devmem2 0x4804403C w 0xFFFFAFFF

# Set the re-load value
#devmem2 0x48044040 w 0xFFFFDFFF
devmem2  0x48048040 w 0xFFFFFD39
# Setting a duty cycle to 50.7%
#devmem2 0x4804404C w 0xFFFFFAF0
devmem2 0x4804804c w 0xFFFFFE9C

#set trigger
devmem2 0x48048044 w 0x00000000
# Force the Timer to Smart-Idle
#devmem2 0x48044010 w 0x8
devmem2 0x48048010 w 0x8
# Start Timer
devmem2 0x48048038 w 0x86F

# Verify that the timer is running,
# by polling the count register a
# few times. We should we up counting.
#for i in {1..2}
#do
 echo "Timer Value $i"
 devmem2 0x4804803C

# End
echo "Timer is Running!"
echo ""
echo "See TP31 on the EVM"
echo ""

# Delay added to allow time for the first timer
# overflow to occur, before any consecutive memory
# accesses are made. (Just for standby testing).

sleep 1

#done

# Disable MODULEMODE of CM_PER_TIMER4_CLKCTRL register
# Only if this value is 0, are we able to wake-up from standby??
devmem2 0x44e000f0 w 0x0

#END