TI ARM Assembler Unix v18.12.3 Mon Sep 30 16:39:01 2019 Copyright (c) 1996-2018 Texas Instruments Incorporated ../main.asm PAGE 1 1 .global main 2 3 00000000 .data 4 00000000 Var1: 5 00000000 E000ED88 .word 0E000ED88h, 01h, 02h, 03h, 04h, 05h, 06h, 07h 00000004 00000001 00000008 00000002 0000000c 00000003 00000010 00000004 00000014 00000005 00000018 00000006 0000001c 00000007 6 ;put your variables here 7 8 00000020 .thumb ; use thumb, UAL syntax 9 10 00000000 .text 11 ; set memory location to flash 12 00000000 main: 13 00000000 E01C b Ldr_ex ; [ORIG 16-BIT INS] 14 00000002 Mov_ex: 15 00000002 0023F04F mov R0, #23h ; [KEEP 32-BIT INS] 16 00000006 1C01 movs R1, R0 ; APSR (Z flag) affected due to s suffix ; [ORIG 16-BIT INS] 17 00000008 0000F04F mov R0, #0 ; [KEEP 32-BIT INS] 18 0000000c 8100F3EF mrs R1, apsr ; read apsr ; [KEEP 32-BIT INS] 19 00000010 2200 movs R2, #0 ; [ORIG 16-BIT INS] 20 ;mov r4, #1234 21 00000012 2634F241 movw R6, #1234h ;way to load 32 bit value in a register ; [KEEP 32-BIT INS] 22 00000016 7665F2C8 movt R6, #8765h ; [KEEP 32-BIT INS] 23 0000001a 0201EA6F mvn R2, R1 ; [KEEP 32-BIT INS] 24 0000001e 7A10EE00 vmov S0, r7 ; Floating point instructions Project propoerties ; [KEEP 32-BIT INS] 25 ; Compiler optons->processor option-> FP support 26 ;ldr r0, var1 ; Observe the encoding of this instruction 27 00000022 0000F240 movw R0, #0 ; [KEEP 32-BIT INS] 28 00000026 0000F2C2 movt R0, #2000h ; [KEEP 32-BIT INS] 29 0000002a 6801 ldr R1, [R0] ; [ORIG 16-BIT INS] 30 0000002c 0100F2C0 movt R1, #00 ; Enable FPU: 0f0h, Disable FPU: 00h ; [KEEP 32-BIT INS] 31 00000030 6001 str R1, [R0] ; [ORIG 16-BIT INS] 32 00000032 1A10EE00 vmov S0, R1 ; [KEEP 32-BIT INS] 33 00000036 0A00EEF7 vmov.f32 S1, #1.0 ; [KEEP 32-BIT INS] 34 0000003a here_m: 35 0000003a E7FE b here_m ; [ORIG 16-BIT INS] 36 37 0000003c Ldr_ex: 38 0000003c 0000F85F ldr r0, Var1 ; Load address of label cpacr in R0 ; [KEEP 32-BIT INS] "../main.asm", ERROR! at line 38: [E0001] Address must be defined in the current section "../main.asm", ERROR! at line 38: [E0004] Illegal operand 39 00000040 0000F240 movw r0, #0 ; [KEEP 32-BIT INS] 40 00000044 0000F2C2 movt r0, #2000h ; [KEEP 32-BIT INS] 41 00000048 6841 ldr R1,[R0, #04h] ; Immediate offset ; [ORIG 16-BIT INS] 42 0000004a 2F08F850 ldr R2,[R0, #08h]! ; Immediate offset with writeback ; [KEEP 32-BIT INS] 43 0000004e 74C2 strb r2, [r0, #13h] ; [ORIG 16-BIT INS] 44 45 00000050 0000F2AF adr r0, Var1 ; Restore R0 ; [KEEP 32-BIT INS] "../main.asm", ERROR! at line 45: [E0001] Address must be defined in the current section TI ARM Assembler Unix v18.12.3 Mon Sep 30 16:39:01 2019 Copyright (c) 1996-2018 Texas Instruments Incorporated ../main.asm PAGE 2 "../main.asm", ERROR! at line 45: [E0004] Illegal operand "../main.asm", ERROR! at line 45: [E0001] Address must be defined in the current section 46 00000054 0000F240 movw r0, #0 ; [KEEP 32-BIT INS] 47 00000058 0000F2C2 movt r0, #2000h ; [KEEP 32-BIT INS] 48 0000005c 1A03EDD0 vldr.32 s3, [r0, #0ch] ; Loading floating point register ; [KEEP 32-BIT INS] 49 50 00000060 0201F04F mov r2, #01 ; [KEEP 32-BIT INS] 51 00000064 5883 ldr r3, [r0, r2] ; register Offset ; [ORIG 16-BIT INS] 52 00000066 0032F840 str r0, [r0, r2, LSL #3] ;scaled register offset ; [KEEP 32-BIT INS] 53 54 0000006a 4B04F850 ldr r4, [r0], #04 ;post-index addressing mode ; [KEEP 32-BIT INS] 55 56 0000006e 0000F240 movw r0, #0 ; load and store multiple ; [KEEP 32-BIT INS] 57 00000072 0000F2C2 movt r0, #2000h ; [KEEP 32-BIT INS] 58 00000076 001EE890 ldmia r0, {r1-r4} ; [KEEP 32-BIT INS] 59 60 0000007a 0020F240 movw r0, #20h ; [KEEP 32-BIT INS] 61 0000007e 0000F2C2 movt r0, #2000h ; [KEEP 32-BIT INS] 62 00000082 001EE920 stmdb r0!, {r1-r4} ; [KEEP 32-BIT INS] 63 64 00000086 0B04EC90 vldmia.64 r0, {D0-D1} ; [KEEP 32-BIT INS] 65 66 0000008a 0100F248 movw r1, #8000h ; [KEEP 32-BIT INS] 67 0000008e 0100F2C2 movt r1, #2000h ; [KEEP 32-BIT INS] 68 00000092 8808F381 msr msp, r1 ; [KEEP 32-BIT INS] 69 70 00000096 here_l: 71 00000096 E7FE b here_l ; [ORIG 16-BIT INS] 72 73 .end -------------------------- Thumb2 Statistics -------------------------- Number of Thumb2 ins converted to Thumb = 0 (0%) Number of Thumb ins in input = 14 (29%) Number of Thumb2 ins encoded as Thumb2 = 33 (100%) Number of Thumb2 ins converted to 2 OPND Thumb = 0 5 Assembly Errors, No Assembly Warnings