lr = 0x0000BEDF pc = 0x00001342 void DL_SYSCTL_configSYSPLL(DL_SYSCTL_SYSPLLConfig *config) { /* PLL configurations are retained in lower reset levels. Set default * behavior of disabling the PLL to keep a consistent behavior regardless * of reset level. */ DL_SYSCTL_disableSYSPLL(); /* Check that SYSPLL is disabled before configuration */ while ((DL_SYSCTL_getClockStatus() & (DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) != (DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) { ; } // set SYSPLL reference clock DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0, ((uint32_t) config->sysPLLRef), SYSCTL_SYSPLLCFG0_SYSPLLREF_MASK); // set predivider PDIV (divides reference clock) DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1, ((uint32_t) config->pDiv), SYSCTL_SYSPLLCFG1_PDIV_MASK); // save CPUSS CTL state and disable the cache uint32_t ctlTemp = DL_CORE_getInstructionConfig(); DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED, DL_CORE_LITERAL_CACHE_ENABLED); // populate SYSPLLPARAM0/1 tuning registers from flash, based on input freq SYSCTL->SOCLOCK.SYSPLLPARAM0 = *(volatile uint32_t *) ((uint32_t) config->inputFreq); SYSCTL->SOCLOCK.SYSPLLPARAM1 = *(volatile uint32_t *) ((uint32_t) config->inputFreq + (uint32_t) 0x4); // restore CPUSS CTL state CPUSS->CTL = ctlTemp; // set feedback divider QDIV (multiplies to give output frequency) DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1, ((config->qDiv << SYSCTL_SYSPLLCFG1_QDIV_OFS) & SYSCTL_SYSPLLCFG1_QDIV_MASK), SYSCTL_SYSPLLCFG1_QDIV_MASK); // write clock output dividers, enable outputs, and MCLK source to SYSPLLCFG0 DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0, (((config->rDivClk2x << SYSCTL_SYSPLLCFG0_RDIVCLK2X_OFS) & SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK) | ((config->rDivClk1 << SYSCTL_SYSPLLCFG0_RDIVCLK1_OFS) & SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK) | ((config->rDivClk0 << SYSCTL_SYSPLLCFG0_RDIVCLK0_OFS) & SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK) | config->enableCLK2x | config->enableCLK1 | config->enableCLK0 | (uint32_t) config->sysPLLMCLK), (SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK | SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK | SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK | SYSCTL_SYSPLLCFG0_ENABLECLK2X_MASK | SYSCTL_SYSPLLCFG0_ENABLECLK1_MASK | SYSCTL_SYSPLLCFG0_ENABLECLK0_MASK | SYSCTL_SYSPLLCFG0_MCLK2XVCO_MASK)); // enable SYSPLL SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_SYSPLLEN_ENABLE; // wait until SYSPLL startup is stabilized while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_SYSPLLGOOD_MASK) != DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD) { ; } } 0x000012e8: f7 b5 push {r0, r1, r2, r4, r5, r6, r7, lr} 0x000012ea: 33 4b ldr r3, [pc, #204] @ (0x13b8 ) -> r3 = SYSCTL_BASE 0x000012ec: 33 4a ldr r2, [pc, #204] @ (0x13bc ) 0x000012ee: 34 4c ldr r4, [pc, #208] @ (0x13c0 ) 0x000012f0: 99 58 ldr r1, [r3, r2] 0x000012f2: 21 40 ands r1, r4 0x000012f4: 99 50 str r1, [r3, r2] - DL_SYSCTL_disableSYSPLL(); 0x000012f6: 80 21 movs r1, #128 @ 0x80 0x000012f8: c9 01 lsls r1, r1, #7 0x000012fa: 32 4c ldr r4, [pc, #200] @ (0x13c4 ) 0x000012fc: 1c 59 ldr r4, [r3, r4] 0x000012fe: 0c 42 tst r4, r1 0x00001300: fb d0 beq.n 0x12fa - while ((DL_SYSCTL_getClockStatus() & (DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) != (DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) {... 0x00001302: 01 26 movs r6, #1 - DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0, - Start 0x00001304: 03 27 movs r7, #3 0x00001306: 30 49 ldr r1, [pc, #192] @ (0x13c8 ) 0x00001308: 44 7e ldrb r4, [r0, #25] 0x0000130a: 0d 68 ldr r5, [r1, #0] 0x0000130c: 6c 40 eors r4, r5 0x0000130e: 34 40 ands r4, r6 0x00001310: 6c 40 eors r4, r5 0x00001312: 0c 60 str r4, [r1, #0] - DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0, - End 0x00001314: 2d 4c ldr r4, [pc, #180] @ (0x13cc ) - DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1, - Start 0x00001316: 45 1c adds r5, r0, #1 0x00001318: 26 68 ldr r6, [r4, #0] 0x0000131a: ed 7f ldrb r5, [r5, #31] 0x0000131c: 75 40 eors r5, r6 0x0000131e: 3d 40 ands r5, r7 0x00001320: 75 40 eors r5, r6 0x00001322: 98 26 movs r6, #152 @ 0x98 0x00001324: 25 60 str r5, [r4, #0] - DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1, - End 0x00001326: 2a 4d ldr r5, [pc, #168] @ (0x13d0 ) - uint32_t ctlTemp = DL_CORE_getInstructionConfig() - Start -> r5 = 0x4040 0x00001328: 76 01 lsls r6, r6, #5 -> r6 = 0x98 << 5 = 0x1300 0x0000132a: af 59 ldr r7, [r5, r6] -> r7 = CPUSS->CTL 0x0000132c: b4 46 mov r12, r6 0x0000132e: 07 26 movs r6, #7 0x00001330: 37 40 ands r7, r6 -> r7 = CPUSS->CTL & (CPUSS_CTL_ICACHE_MASK | CPUSS_CTL_PREFETCH_MASK | CPUSS_CTL_LITEN_MASK) 0x00001332: 01 97 str r7, [sp, #4] - uint32_t ctlTemp = DL_CORE_getInstructionConfig() - End 0x00001334: 67 46 mov r7, r12 0x00001336: 02 3e subs r6, #2 0x00001338: ee 51 str r6, [r5, r7] - DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED, DL_CORE_LITERAL_CACHE_ENABLED); - End 0x0000133a: 46 6a ldr r6, [r0, #36] @ 0x24 -> r6 = config->inputFreq 0x0000133c: 37 68 ldr r7, [r6, #0] -> r7 = *config->inputFreq 0x0000133e: 3d 00 movs r5, r7 -> r5 = r7 0x00001340: 24 4f ldr r7, [pc, #144] @ (0x13d4 ) -> r7 = &SYSCTL->SOCLOCK.SYSPLLPARAM0 0x00001342: dd 51 str r5, [r3, r7] <--- PC reported in hard fault, write r5 to r3+r7 SYSCTL->SOCLOCK.SYSPLLPARAM0 = 0x00001344: 65 46 mov r5, r12 0x00001346: 77 68 ldr r7, [r6, #4] 0x00001348: 23 4e ldr r6, [pc, #140] @ (0x13d8 ) 0x0000134a: 9f 51 str r7, [r3, r6] - SYSCTL->SOCLOCK.SYSPLLPARAM1 = - End 0x0000134c: 01 9e ldr r6, [sp, #4] - CPUSS->CTL = ctlTemp; Start 0x0000134e: 20 4f ldr r7, [pc, #128] @ (0x13d0 ) 0x00001350: 7e 51 str r6, [r7, r5] - CPUSS->CTL = ctlTemp; End 0x00001352: fe 27 movs r7, #254 @ 0xfe 0x00001354: c5 69 ldr r5, [r0, #28] 0x00001356: 26 68 ldr r6, [r4, #0] 0x00001358: ff 01 lsls r7, r7, #7 0x0000135a: 2d 02 lsls r5, r5, #8 0x0000135c: 3d 40 ands r5, r7 0x0000135e: 75 40 eors r5, r6 0x00001360: 3d 40 ands r5, r7 0x00001362: f0 27 movs r7, #240 @ 0xf0 0x00001364: 75 40 eors r5, r6 0x00001366: 25 60 str r5, [r4, #0] 0x00001368: 06 69 ldr r6, [r0, #16] 0x0000136a: c5 68 ldr r5, [r0, #12] 0x0000136c: 3f 03 lsls r7, r7, #12 0x0000136e: 35 43 orrs r5, r6 0x00001370: 46 69 ldr r6, [r0, #20] 0x00001372: 0c 68 ldr r4, [r1, #0] 0x00001374: 35 43 orrs r5, r6 0x00001376: 06 7e ldrb r6, [r0, #24] 0x00001378: 35 43 orrs r5, r6 0x0000137a: 06 68 ldr r6, [r0, #0] 0x0000137c: 36 04 lsls r6, r6, #16 0x0000137e: 3e 40 ands r6, r7 0x00001380: 35 43 orrs r5, r6 0x00001382: 46 68 ldr r6, [r0, #4] 0x00001384: 80 68 ldr r0, [r0, #8] 0x00001386: 36 07 lsls r6, r6, #28 0x00001388: 36 0c lsrs r6, r6, #16 0x0000138a: 35 43 orrs r5, r6 0x0000138c: f0 26 movs r6, #240 @ 0xf0 0x0000138e: 00 02 lsls r0, r0, #8 0x00001390: 36 01 lsls r6, r6, #4 0x00001392: 30 40 ands r0, r6 0x00001394: 28 43 orrs r0, r5 0x00001396: 11 4d ldr r5, [pc, #68] @ (0x13dc ) 0x00001398: 60 40 eors r0, r4 0x0000139a: 28 40 ands r0, r5 0x0000139c: 60 40 eors r0, r4 0x0000139e: 08 60 str r0, [r1, #0] 0x000013a0: 80 21 movs r1, #128 @ 0x80 0x000013a2: 98 58 ldr r0, [r3, r2] 0x000013a4: 49 00 lsls r1, r1, #1 0x000013a6: 01 43 orrs r1, r0 0x000013a8: 99 50 str r1, [r3, r2] 0x000013aa: 80 22 movs r2, #128 @ 0x80 0x000013ac: 92 00 lsls r2, r2, #2 0x000013ae: 05 49 ldr r1, [pc, #20] @ (0x13c4 ) 0x000013b0: 59 58 ldr r1, [r3, r1] 0x000013b2: 11 42 tst r1, r2 0x000013b4: fb d0 beq.n 0x13ae while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_SYSPLLGOOD_MASK) != DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD) { ... 0x000013b6: f7 bd pop {r0, r1, r2, r4, r5, r6, r7, pc} return; Addresses - loaded via ldr rX, [pc, #xxx] instructions 0x000013b8: 00 f0 0a 40 and.w r0, r0, #2315255808 @ 0x8a000000 -> SYSCTL, SYSCTL_BASE 0x000013bc: 08 11 asrs r0, r1, #4 -> SYSCTL->SOCLOCK.HSCLKEN 0x000013be: 00 00 movs r0, r0 0x000013c0: ff fe ff ff mrc2 15, 7, pc, cr15, cr15, {7} 0x000013c4: 04 12 asrs r4, r0, #8 -> SYSCTL->SOCLOCK.CLKSTATUS 0x000013c6: 00 00 movs r0, r0 0x000013c8: 20 01 lsls r0, r4, #4 0x000013ca: 0b 40 ands r3, r1 0x000013cc: 24 01 lsls r4, r4, #4 0x000013ce: 0b 40 ands r3, r1 0x000013d0: 00 00 movs r0, r0 0x000013d2: 40 40 eors r0, r0 -> Upper 16-bit of CPUSS->CTL 0x000013d4: 28 11 asrs r0, r5, #4 -> SYSCTL->SOCLOCK.SYSPLLPARAM0 0x000013d6: 00 00 movs r0, r0 0x000013d8: 2c 11 asrs r4, r5, #4 -> SYSCTL->SOCLOCK.SYSPLLPARAM1 0x000013da: 00 00 movs r0, r0 0x000013dc: 72 ff 0f 00 vhadd.u d16, d2, d15