# AM64x\AM62x\AM243x\AM62Ax DDR Register Configuration (v9.05)

## Procedure:
1) Select Add button at the top and choose the DDR Memory Type.  Fields will be populated with default values for AM64x\AM62x\AM243x\AM62Ax EVMs<br>
2) Modify parameters based on your DDR device. Hover mouse pointer over each parameter and choose the help icon (?) for more explanation<br>
3) The 'Generated Files' section on the right has output files for your software (uboot, RTOS, or GEL) that can be saved.  A SysConfig configuration script can also be saved and then reloaded at a later time using File->Open in Sysconfg.

### GEL
The resulting .gel file should be placed in the CCS installation for your device, for example ccs\ccs_base\emulation\gel\AM64x\AM64_DDRSS, and loaded using a GEL_LoadGEL instruction (see example in ccs\ccs_base\emulation\gel\AM64x\AM64_DDRSS\AM64x_GP_EVM.gel)

### CMM
The resulting .cmm file should be placed in the Lautherbach installation for your device.

### Linux u-boot
The resulting .dtsi file should be placed in arch/arm/dts, and the include statement in k3-am642-r5-<board>.dts (eg., k3-am642-r5-evm.dts for the GP EVM, or k3-am642-r5-sk.dts for the StarterKit) should reference the new .dtsi file.  The DDR driver will properly set the DDR frequency and initialize the DDR controller using the information in this .dtsi file

### MCU+ SDK (RTOS)
The resulting .h file should be placed in mcu_plus_sdk_<device>_<version>\source\drivers\ddr\v0\soc\am64x_am243x  
and included by using the SysConfig for SDK tool when building your code.  Please refer to the SDK API Guide mcu_plus_sdk_<device>_<version>\docs\api_guide_am64x\DRIVERS_DDR_PAGE.html for more information

## Revision History
v8.10: initial stable version.  Changes from previous versions include:
- added read/write DBI selection for LPDDR4/DDR4.  Default to enable write DBI for LPDDR4, read DBI for DDR4 to improve power supply noise and improve overall signal integrity
- changed default value of CA ODT to 60ohm for both LPDDR4 and DDR4
- updated RTOS output to fix #ifdef
- periodic write DQ leveling disabled to improve realtime performance
- disabled "always-on" mode of the input enables for data bytes for power optimization
- disabled VREF controller for addr/cmd signals for power optimization<br>
  
v8.40: provides improved operation at 1600MTs for both LPDDR4 and DDR4.  Changes from previous version include:
- changed default value CTRLUPD_AREF_HP_ENABLE=0
- changed default value LPI_WAKEUP_EN=0
- changed cal_clk divider and PVT calibration interval.  This change provides significant stability improvements for LPDDR4 and DDR4 operation at 1600MTs
- fixed TOSCO_F0 calculation for LPDDR4
  
v8.80: added support for AM62x release, added support for high temp operation, Other misc fixes to align with documentation: 
- CTL_165[11]=1 (LPI_WAKEUP_EN) only applicable for AM62x
- CTL_321[23:8] = 0xFFFF (CS_MSK_1) corrected value when rank 1 disabled

v9.04: 
-changed wrlvl_delay_early_threshold=0x100 to allow write leveling to complete successfully for wider array of layouts<br> 
-add cmm output<br>
-LPDDR4: phy_rddqs_latency_adjust changed to 0 default recommendation (this value gets optimized during training)<br> 
-LPDDR4: optimized training loops to support 1 operating frequency<br>
-LPDDR4/DDR4: optimized IO calibration configuration based on operating frequency<br>
-LPDDR4/DDR4: optimized internal calibration clock based on operating frequency<br>
-LPDDR4: changed default MR22 ODTE-CS=1<br>
-LPDDR4: changed rx_ctle_cs default to No Boost<br>
-AM62x dual rank support<br>
-updated to use sysconfig v1.15<br>
-public release for AM62A LPDDR4 support<br>
v9.05:
-cleaned up supported frequencies