/*
 * SitaraMcuIsolation.hpp
 *
 *  Created on: 26.11.2024
 *      Author: zhih
 */

#ifndef SITARAMCUISOLATION_HPP_
#define SITARAMCUISOLATION_HPP_

#include "CommonTypes.hpp"

namespace balluff
{
namespace bni_safe
{
namespace pal
{
namespace sitara
{

class SitaraMcuIsolation
{
  public:
    SitaraMcuIsolation();
    ~SitaraMcuIsolation();

  private:
    util::SafeReturn enableResetIsolation(uint32_t main2McuIsolation, uint32_t mcu2MainIsolation,
                                          uint32_t debugIsolationEnable);
    util::SafeReturn setPSCState(uint32_t moduleNum, uint32_t pscState);

    void controlModuleLockMMR(uint32_t partition);
    void controlModuleUnlockMMR(uint32_t partition);

    static uint32_t REG32_RD(uint32_t addr)
    {
        volatile uint32_t* const p = (volatile uint32_t*)addr;
        return (*p);
    }
    static void REG32_WR(uint32_t addr, uint32_t v)
    {
        volatile uint32_t* const p = (volatile uint32_t*)addr;
        *p = v;
        return;
    }

    static void REG32_FINS(uint32_t addr, uint32_t mask, uint32_t shift, uint32_t v)
    {
        uint32_t regVal = REG32_RD(addr);
        regVal = (regVal & ~(mask));
        regVal |= (v << shift) & mask;
        REG32_WR(addr, regVal);
        return;
    }

    static uint32_t REG32_FEXT(uint32_t addr, uint32_t mask, uint32_t shift)
    {
        uint32_t regVal = REG32_RD(addr);
        regVal = (regVal & mask) >> shift;
        return (regVal);
    }

    static constexpr uint32_t CSL_MCU_CTRL_MMR0_CFG0_BASE = 0x04500000U;
    static constexpr uint32_t CSL_MCU_CTRL_MMR_CFG0_MCU_MTOG_CTRL = 0x00004600U;
    static constexpr uint32_t CSL_MCU_CTRL_MMR_CFG0_RST_CTRL = 0x00018170U;
    static constexpr uint32_t CSL_MCU_CTRL_MMR_CFG0_RST_MAGIC_WORD = 0x0001817CU;
    static constexpr uint32_t CSL_MCU_CTRL_MMR_CFG0_ISO_CTRL = 0x00018180U;

    static constexpr uint32_t CSL_MCU_PSC0_BASE = 0x04000000U;
    static constexpr uint32_t CSL_MCU_PSC0_PTCMD = 0x00000120U;
    static constexpr uint32_t CSL_MCU_PSC0_PTSTAT = 0x00000128U;
    static constexpr uint32_t CSL_MCU_PSC0_PDCTL = 0x00000300U;
    static constexpr uint32_t CSL_MCU_PSC0_MDSTAT = 0x0000080CU;
    static constexpr uint32_t CSL_MCU_PSC0_MDCTL = 0x00000A00U;


    static constexpr uint32_t SOC_PSC_SYNCRESETDISABLE = 0x0U;
    static constexpr uint32_t SOC_PSC_SYNCRESET = 0x1U;
    static constexpr uint32_t SOC_PSC_DISABLE = 0x2U;
    static constexpr uint32_t SOC_PSC_ENABLE = 0x3U;

    /*
     *  MCU LPSC
     */
    static constexpr uint32_t CSL_MCU_LPSC_MAIN2MCU = 0x3U;
    static constexpr uint32_t CSL_MCU_LPSC_MCU2MAIN = 0x4U;


    /* PSC (Power Sleep Controller) timeout */
    static constexpr uint32_t PSC_TIMEOUT = 1000U;

    /* PSC (Power Sleep Controller) Domain enable */
    static constexpr uint32_t PSC_MODSTATE_ENABLE = 0x3U;

    /* define the unlock and lock values */
    static constexpr uint32_t KICK_LOCK_VAL = 0x00000000U;
    static constexpr uint32_t KICK0_UNLOCK_VAL = 0x68EF3490U;
    static constexpr uint32_t KICK1_UNLOCK_VAL = 0xD172BC5AU;
};

} // namespace sitara

} // namespace pal

} // namespace bni_safe

} // namespace balluff

#endif /* SITARAMCUISOLATION_HPP_ */