• Timing is Everything: Design JESD204B clocking using system reference modes

  

  Julian Hagedorn

  Other Parts Discussed in Post: LMK04821 Hello and welcome back to the “ Timing is Everything ” blog series. In a previous post , Timothy T. talked about the clocking requirements of the JESD204B interface standard that is gaining popularity for…

  • over 7 years ago
  • Technical articles
  • Analog

• Timing is Everything: Improving integer boundary spurs in fractional PLL synthesizers

  

  Dean Banerjee

  Have you ever done a phase-locked loop (PLL) design with a fractional synthesizer that looked great at integer channels, but then the spurs got much higher on frequencies that were just slightly offset from those integer channels? If so, you have experienced…

  • over 7 years ago
  • Technical articles
  • Analog

• Timing is Everything: Jitter specifications

  

  Gabe Ayala

  Welcome back to Timing is Everything! Last time we covered Understanding PLL loop filter response . Today, I will be helping you learn how to better understand the variety of jitter specifications. As timing requirements in high-speed applications become…

  • over 8 years ago
  • Technical articles
  • Analog

• Timing is Everything: JESD204B subclass 1 clocking timing requirements

  

  Timothy T

  Most of the JESD204B standard addresses the data interface between logic devices and converters, so what are the clocking requirements? For JESD204B subclass 1, the clocking requirement is quite simple: use the SYSREF rising edge to mark the device clock…

  • over 8 years ago
  • Technical articles
  • Analog

• Timing is Everything: Understanding LVPECL and a newer LVPECL-like output driver

  

  Mike Wang2

  Welcome to our Timing is Everything series ! Today we will talk about the low-voltage positive emitter-coupled logic (LVPECL) since it’s a very popular signal type. In this blog, we’ll go through some key features of LVPECL, its advantages and disadvantages…

  • over 8 years ago
  • Technical articles
  • Analog

• Timing is Everything: Understanding PLL loop filter response

  

  Noel Fung

  Welcome back to Timing is Everything! Last time in our series, we covered how to measure additive jitter . Today, I will be discussing phase lock loop (PLL) systems and how to understand PLL loop filter response. A PLL system consists of a stable and…

  • over 8 years ago
  • Technical articles
  • Analog

• Timing is Everything: I need a clock, can you help?

  

  Brian Wang

  Welcome back to our Timing is Everything clock series! Today I will be covering how to select the clock or timing IC that best fits your application . It’s a fair question to ask: “Is there more to choosing a clock than to just pick one that produces the…

  • over 8 years ago
  • Technical articles
  • Analog

• Timing is Everything: How to measure additive jitter

  

  Julian Hagedorn

  Welcome to the first blog in our new Timing is Everything series ! In this series, you will find all your clock questions and needs addressed by our TI clock experts. I will be kicking off this new series by helping you learn how to correctly measure the…

  • over 8 years ago
  • Technical articles
  • Analog

• Timing is Everything: How to create modulated waveforms using fractional PLLs

  

  Dean Banerjee

  We’ve likely all seen situations where we’ve needed to sweep the frequency over time. If you are faced with this, consider an application like radar where a transmitted signal is bounced off a target and compared to the received signal, as…

  • over 8 years ago
  • Technical articles
  • Analog

• Timing is Everything: How to optimize clock distribution in PCIe applications

  

  Julian Hagedorn

  Puneet Sareen contributed to the updates and additions to this blog in January 2018. PCI Express® (PCIe®) is an industry-leading standard input/output (I/O) technology. It is one of the most commonly used I/O interface in servers, personal computers,…

  • over 9 years ago
  • Technical articles
  • Analog

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