Frequent Questions

  • [FAQ] TDA4VM: How to check Memory properties on R5F core from registers ?

    Part Number: TDA4VM After providing MPU properties in file r5_mpu_freertos.c, how to learn these properties from R5 registers ?

  • [FAQ] CC2745R10-Q1: ADC + BLE on Zephyr

    Part Number: CC2745R10-Q1 Other Parts Discussed in Thread: CC2755R10 This post presents three example projects demonstrating incremental BLE functionality on the TI CC2755 microcontroller using Zephyr 3.7.0 v3.7.0-ti-9.14.00_ea. All projects use:…

  • [FAQ] TDA4VH-Q1: TISCI_DEV_ID mapping to ECC Aggregator

    Part Number: TDA4VH-Q1 Which TISCI_DEV_IDs must be enabled for each of the ECC aggregators? Please provide a mapping.

  • [FAQ] Troubleshoot Guide for McSPI within Linux: J784S4/AM6x/TDA4x/DRA8x

    Part Number: J784S4XEVM Other Parts Discussed in Thread: DRA821 , TDA4VL , AM68 , TDA4VM , TDA4VH How do I troubleshoot the McSPI interface within Linux? McSPI is not working or partially working.

  • [FAQ] AM62A7: How do I update the AM62A memory map?

    Part Number: AM62A7 Q: The default memory map for AM62A does not work for my application. How do I modify the RAM / DDR memory map to suit my module size and application?

  • [FAQ] TPS546E25: FAQ Which version of FUSION GUI supports TPS546E25 and where to get it?

    Part Number: TPS546E25 Which version of FUSION GUI supports TPS546E25 and where to get it? TI FUSION Digital Power Designer 7.10.5 and later supports TPS546E25 Version 7.10.17 is available here Link to Product Folder Go to TPS546E25 Folder…

  • [FAQ] AM6442: ROV throwing exception for NoLoad memory section

    Part Number: AM6442 I am Runtime Object View in my application and it throws expection when I keep Heap section into the NoLoad memory region. Note: The issue is specific to CCS Eclipse based IDE (CCS v12.8.1). Please refer below error message…

  • [FAQ] PGA900: How do I communicate with PGA900/PGA970 when the compensation algorithm is running using the COMBUF?

    Part Number: PGA900 I want to read data from the ADCs or the compensation algorithm, or any other register while the PGA900/970 is running. Most registers can only be read/written while the device is in reset, and they are inaccessible while the device…

  • [FAQ] AM62A7-Q1: Bring Your Own Model Deployment on AM62A in an end-to-end pipeline (GStreamer) with custom postprocessing

    Part Number: AM62A7-Q1 I have successfully compiled a neural network model with TIDL. Now I want to run it on the processor using GStreamer, but I want to implement my own custom postprocessing. How do I implement this?

  • [FAQ] AM62P-Q1: Continuous Data Streaming over UART using DMA

    Part Number: AM62P-Q1 Continuous Data Streaming over UART is a use-case across different applications. Lets check the implementation and any additional pointers to take care of while implementing this. This FAQ applies to other SoCs as well like AM62x…

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