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LOG101: Output signals have ripples

ArTzy
Genius 15769 points
Part Number: LOG101

Hi Experts,

Seeking your assistance on this query from Cx:

They have two problems with LOG101.

  1. Output of LOG101 have ripple in the upper voltage decades.
  2. Output voltage amplitude shifts up and down on base input current.

Problem 1:

In first step they connected LOG101 as is notice in datasheet.

  • Vcc = ±10V (20V)
  • Cc = 47pF
  • I1 = 10µA
  • I2 = sawtooth amplitude0-10V / 1Mohm
  • F_I2 = DC to 100Hz.

Noticed that LOG101 output had ripple in the upper voltage decades.

In second step they connected LOG101 as in Figure 1 below.

Noticed that its output had even bigger ripple in the upper voltage decades as before in first step. For that reason, they began to reason that the output LOG101 is overloaded and so did another experiment (follow step third).

Figure 1:

In third step they connected LOG101 as in Figure 2 below (with output buffer).

Noticed that LOG101 output had the same ripple in the upper voltage decades as before in first step. The problem is that the output is oscillating on upper voltage decades.

They have a theory that it is overloaded by a capacitor Cc that prevents oscillation in the lower decades.

The connection is not on the PCB, but with short wires, the shortest way. If the problem was induction, it would be most noticeable at low currents and not at high currents.

Figure 2:

 

Problem 2:

Output voltage amplitude shifts up and down on base input current.

If they use a symmetrical amplifier at the output of LOG101, the amplitude of the symmetrical amplifier reaches saturation in the lower or upper decade, because LOG101 shifts the output on base input current range.

In addition, the LOG101 does not have 8Vpp at the output as stated in the datasheet, but only something around 4V, which I am trying to amplify to +-10V. Their question is why does the amplitude move up or down?

For your assistance please.

Thank you.

Regards,
Archie A.

  • 0
    TI__Guru 54566 points

    Hi Archie,

    I am out of office today, but expect to look into this case late this evening.  I expect to get back to you by Monday mid afternoon at the latest.

    Thank you and Regards,

    Luis

  • 0 in reply to Luis Chioye
    TI__Genius 15769 points

    Hello Luis,

    Thank you and looking forward to your judgment.

    Happy weekend.

    Regards,
    Archie A.

  • 0
    Guru 140200 points

    Hi Archie,

    have you accidentally mixed-up the two inputs?

    Kai

  • 0
    Guru 140200 points

    Hi Archie,

    your scope plot should look like this:

    archie_log101.TSC

    But your scope plot is more looking like this, indicating that the inputs are mixed-up:

    Keep in mind that a LOG amplifier is no simple OPAmp. The characteristics of the internal LOG transistors extremely depend on the collector currents flowing through them. It is like having a complete different circuit at low collector currents and high collector currents. Because of this a LOG amplifier is one of the most complicated circuits of all. And if you drive the input of LOG101 by a signal showing a steep high to low edge as in your case with the sawtooth with an input current going all the way down to zero, you may see a very weird performance.

    ArTzy said:
    In addition, the LOG101 does not have 8Vpp at the output as stated in the datasheet, but only something around 4V

    This has to do with the fact that the maximum output voltage the LOG101 is able to give corresponds with a zero input current. But with a zero input current the 47pF cap cannot be fully discharged. This would take an infinitely long time. Only the input bias current (input leakage current) of LOG101 in the pA range is able to do this. So you have to wait a very very long time, especially because with your input signal the input current is zero only for a very brief period. So, the maximum output voltage can only be seen with a very very large period of you input signal:

    Keep in mind that driving the input current to zero means for a LOG amplifier to enter the "no man's land". A zero input current for a LOG amplifier is like a "black hole" in astronomy.

    Kai

  • 0 in reply to kai klaas69
    TI__Guru 54566 points

    Hi Archie,

    Have you confirmed the connections of I1 and I2 as Kai has suggested, or are they reversed in the setup?

    The LOG101 amplifier input I1 requires an input current flowing into the device.  A current of IREF=~0uA will not bias the internal A1 amplifier properly, where A1 may not have the correct feedback.

    Thank you and Regards,

    Luis

  • +1 in reply to Luis Chioye
    TI__Guru 54566 points

    HI Archie,

    The LOG101 will only work with positive currents flowing into pins 1 an pin 8, as the internal transistors Q1, Q2 need to be biased correctly.  The device will not work with negative currents or currents close to 0. The device performance is specified for input currents as low as I1 = I2 = 100pA flowing into the device. Let me know if you have further questions. From p. 6 of the LOG101 datasheet:

    Thank you and Regards,

    Luis

  • 0 in reply to Luis Chioye
    TI__Genius 15769 points

    Hello Luis,

    Thanks for your answer. We now understand for all.

    We use I1 s reference input, but irrelevant. Whether the waveform is inverted or not, it is not a situation we want to deal with.

    Follow up question:
    We are     wondering why the amplifier oscillates at high currents?

    Thank you.

    Regards,
    Archie A.

  • 0 in reply to ArTzy
    TI__Guru 54566 points

    Hi Archie,

    On step 3, per your explanation, they are using the ADA8404 buffer, hence there would be no output load capacitance causing in-stability.  

    The datasheet specifies the I2 = 10uA frequency response using a more conservative ~150pF compensation capacitor:  

       -  Have they attempted increasing the compensation capacitor to 150pF?

    You have mentioned that the connection is not on the PCB, using short wires. 

    -  Are the 1-MΩ resistors placed on the PCB right next to the pins of the LOG101 or are these connected through wires?  If I1 reference is 10uA (fixed), and I2 max is 10uA, the minimum capacitance required is in the >10pF range per the "MINIMUM VALUE OF COMPENSATION CAPACITOR" figure on page 4, but this figure assumes an optimal board layout where the PCB setup and stray capacitances are kept very small.

    -  Do you have a picture of the setup?

    Thank you and Regards,

    Luis

  • 0 in reply to ArTzy
    Guru 140200 points

    Hi Archie,

    I think the LOG101 could already have been damaged during the experimenting. I would replace it by a fresh one.

    The 47pF cap could also be damaged. Are you sure that it is a NP0 model? Also replace it by a fresh one.

    And what about the supply voltage decoupling? Have you mounted decoupling caps as shown in figure 1 of datasheet?

    Finally, take care that the input voltages aren't applied before the supply voltages of LOG101 have fully stabilized after power-up and -vice versa- that the input voltages are removed (or set to zero) before the LOG101 powers down.

    Kai

  • 0 in reply to kai klaas69
    TI__Guru 54566 points

    HI Archie,

    A picture of the setup, as well as the PCB layout information would be helpful. Assuming there is no significant output load capacitance since the device is buffered, one concern could be stray capacitance at the inputs. 

    Let us know if the issue is occurs on only one device or the issue persists after testing fresh units.

    Thank you and Regards,

    Luis