Hi team,
Could you please help check the clock stretching mechanism of INA3221?
My customer faced the clock stretching issue during using INA3221, and resulting in host wrongly reading the data.
The related waveforms are attached, the clock stretching period is around 80ms.
According to the code pattern calculation, BMC should have mistakenly used the value during clock stretch as valid data (Channel-3 Bus Voltage--high bit 0x03--low bit 0xff), and returned a relatively high result of 1.016V.
