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TLV320AIC3254: Decimation filter in the codec is restricting the digital bandwidth

Lauren Mayfield
Expert 7180 points
Part Number: TLV320AIC3254

In testing the AIC3254, my customer is finding that we can pass the wide band signals through in analog loopback, but the decimation filter in the codec is restricting the digital bandwidth to 20 kHz or so even when the sample rate is 192 kHz. Their engineer is looking at perhaps configuring the mini DSP to change that, but it is slow going, do you have any suggestions for them?

  • 0
    TI__Guru 62765 points

    Hi Lauren,

    Does the customer have an analog filter somewhere in the loopback path?  The bandwidth in 192kHz mode will depend on the filter setting and decimation settings can be seen in Section 2.3.3.1.11 Decimation Filter of the application reference guide:  

    https://www.ti.com/lit/an/slaa408a/slaa408a.pdf

    If they're using Decimation Filter C the bandwidth could be as low as ~21kHz which is about what they're reporting.  Is there a schematic they can share and are they using any additional biquads?

  • 0 in reply to Collin Wells
    TI__Expert 7180 points

    Hey Collin,

    They're using the EVM board TLV320AIC3254EVM-K. They made sure to bypass the low pass filter on the output of LOL by taking the signal directly from that TP9 LOL.

    From what I have read it seems that if they want to sample at 192kHz then they have to use Decimation Filter C with an AOSR of 2. From 2.3.3.1.11.3 it says the pass band extends up to 0.11*fs which is about 21kHz. Although it seems that they can bypass Decimation Filter C by using the miniDSP which gives the option of only a decimation of 1. They are currently working their way through Pure Path Studio in order to do this.

     

  • 0 in reply to Lauren Mayfield
    TI__Guru 62765 points

    Hi Lauren,

    I actually misread the plot and for the calculation and used 0.2*fs instead of 0.11*fs.  You're correct and the with Decimation Filter C the passband is roughly 21kHz as they're suggesting.

    Keep us in the loop on their progress with the PPS developments.

  • 0 in reply to Collin Wells
    TI__Expert 7180 points

    Thanks Collin! That is good to know

    They are actually having an issue with PPS, when they download and run from PPS it changes a lot of their analog and clock settings. PPS is only meant to configure the miniDSP, correct? Is there a reason why it would change their analog settings? Can they change it back to their desired settings and is there a way to prevent this?

  • 0 in reply to Lauren Mayfield
    TI__Guru 62765 points

    Hi Lauren,

    The register settings can be modified using the "Systems settings code" section of PPS.  Click on the "..." expand button and it will open the "SystemSettingsCodeEditor."  Use this to modify the register settings to match the settings of the ADC GUI.

  • 0 in reply to Collin Wells
    TI__Expert 7180 points

    Thank you very much Collin!

    I think they were struggling with not understanding that the sample rate directly determines what decimation factor and framework has to be used. They assumed if they picked a framework it would limit their options to only things that would work, but that is not the case.

    They were able to measure a bandwidth of 31.5kHz when using a sample rate of 192kHz, Framework AIC3254 2x1x, Dec1xIn, and Int2xOut. I internally sent you their Process Flow file which can be opened in PPS and was wondering if you could take a look to see if they are doing anything obviously wrong? They were expecting to get something closer to 80kHz of bandwidth.

    Also, do you have any other thoughts or things they should be looking out for?

    Thank you!
    Lauren

  • 0 in reply to Lauren Mayfield
    TI__Expert 6440 points

    Hi Lauren,

    Could you send out the process flow to me as well? I would also like to see the frequency-response plot. 

    Best Regards.