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LMK04832: About CMOS output from LMK04832

shen jie
Prodigy 215 points
Part Number: LMK04832
Other Parts Discussed in Thread: LMK04208

Tool/software:

Hi,

I just want to configure CLKoutY LMK04832 as CMOS format as below figures shown, and have two questions about it:

1. CMOS(Norm/Norm) means that CLKoutY_P is normal 3.3v LVCOMS Clock output and CLKoutY_N is normal 3.3v LVCOMS Clock output too， right？

2. When CLKoutY is configured as CMOS(Norm/Norm) format, how about skew or delay between CLKoutY_P and CLKoutY_N? 

Thanks in advance！

Best regards！

Jason

  • 0
    TI__Genius 10975 points

    Jason,

    shen jie said:
    1. CMOS(Norm/Norm) means that CLKoutY_P is normal 3.3v LVCOMS Clock output and CLKoutY_N is normal 3.3v LVCOMS Clock output too， right？

    Correct, normal meaning it's not 180 degrees out of phase with the "normal" signal.

    shen jie said:
    2. When CLKoutY is configured as CMOS(Norm/Norm) format, how about skew or delay between CLKoutY_P and CLKoutY_N?

    We do not have the validation data for this, but I would assume is less than 35ps (or less than skew of 2 outputs in the same CLKout pair).

    Best,

    Andrea

  • 0 in reply to Andrea Vallenilla
    Prodigy 215 points

    Hi, Andrea:

    Thanks a lot!

    For question 2, could you please make a measurement if it is convenient for you or you have time? I will appreciate it very much.

    Thanks in advance!

    Best regards!

    Jason

  • 0 in reply to shen jie
    TI__Genius 10975 points

    Jason,

    I'm going OoO tomorrow and won't be back until Monday. I can probably get back to you by next week with this measurement. Note that the value I give you will not be across temperature, parts, process variation, etc. just a one spot check in the lab.

    Best,

    Andrea

  • 0 in reply to Andrea Vallenilla
    Prodigy 215 points

    Hi, Andrea:

    How about this measurement? I hope that you could make two measurements:

    1. the skew between CLKoutY_P and CLKoutY_N when CLKoutY is configured as CMOS(Norm/Norm) format

    2. the skew between CLKoutY1_P and CLKoutY2_P when CLKoutY1 and CLKoutY2  are configured as CMOS(Norm/Norm) format too

    I have this kind of application that let one LMK04832 to provide 14 edge-aligned and LVCMOS pulse signals through configuring total 7 CLKoutYs as CMOS(Norm/Norm) format.

    Thanks in advance!

    Best regards!

    Jason

  • 0 in reply to shen jie
    TI__Prodigy 160 points

    Hi Jason,

    I took measurements for points requested. Please see below:

    1- The skew between CLKoutY_P and CLKoutY_N when CLKoutY is configured as CMOS(Norm/Norm) format

    The reason that there is a delay >35ps is that this config is for LVCMOS output whereas the spec in the datasheet Andrea has mentioned referrers to a differential output (please see note 15 on page 12 of the datasheet) 

    CLKoutY_P and CLKoutY_N when CLKoutY is configured as CMOS(Norm/Norm) format

    2- The skew between CLKoutY1_P and CLKoutY2_P when CLKoutY1 and CLKoutY2 are configured as CMOS(Norm/Norm) format 

     CLKoutY1_P and CLKoutY2_P when CLKoutY1 and CLKoutY2 are configured as CMOS(Norm/Norm) format

    3-The skew of CLKoutY1_P and CLKoutY2_P when Y1 and Y2 are configured to LVPECL format 

    The skew of CLKoutY1_P and CLKoutY2_P when Y1 and Y2 are configured to LVPECL format

    Regards,

    Sandra 

  • 0 in reply to Sandra Saba
    Prodigy 215 points

    Hi, Andrea:

    Get it, thank you very much!

    Yes, you are right, and 35ps in spec just aim at differential format.

    It seems that  the skew between CLKoutY_P and CLKoutY_N or CLKoutY1_P and CLKoutY2_P as LVCMOS format could be controlled <100ps?

    Also I see that frequency under test is 210MHz. If frequency is changed to 10MHz, whether will skew be less?

    Thanks a lot

    Best regards!

    Jason

  • 0 in reply to shen jie
    Prodigy 215 points

    BTW, I see that the vertical scale is 200mV.  The count of grids are eight that means the amplitude is less than 1.6V When LVCMOS output 210MHz frequency. But the spec demand that the VOH could reach to 3.2v based on VCC=3.3v when fCLKout <=250Mhz.  Amplitude of LVCMOS format will decrease obviously when frequency increase as below thread shown. When frequency go down, the edge of signal will be more steep. So, I kindly request you to test 10MHz, let' see if it will get less skew.

    https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1226302/lmk04832-cmos-output-amplitude-attenuation

     

    Thanks a lot!

    Best regards!

    Jason

  • 0 in reply to shen jie
    TI__Prodigy 160 points

    Hi Jason,

    I will get back to you next week with the measurement for 10Mhz 

    Regards,

    Sandra 

  • 0 in reply to Sandra Saba
    Prodigy 215 points

    Hi, Sandra：

    How about the measurement for 10Mhz? 

    Thanks in advance!

    Best regards!

    Jason

  • 0 in reply to shen jie
    TI__Genius 10975 points

    Jason,

    Sandra is planning to go to lab tomorrow to get this measurement for you.

    Best,

    Andrea

  • 0 in reply to Andrea Vallenilla
    Prodigy 215 points

    Hi, Andrea:

    Nice to see your back! I will wait for measurement form Sandra:)

    I check the datasheet of LMK04208, and find that maximum skew between any two LVCMOS outputs, same CLKout or different CLKout is 100ps as below figure.1 shown. It accord with the LMK04232 measurement result of you as below figure.2 shown for.

    Whether could LMK04232 refer to this spec of LMK04208? It seems that LMK04232 and  LMK04208 belong to the same Dual-PLL family

    Thanks a lot!

    Figure.1

    Figure.2

    Best regards!

    Jason

  • 0 in reply to shen jie
    TI__Prodigy 160 points

    Hello,

    Please see below measurements taken at 10MHz.

    1- The skew between CLKoutY_P and CLKoutY_N when CLKoutY is configured as CMOS(Norm/Norm) format

    2- The skew between CLKoutY1_P and CLKoutY2_P when CLKoutY1 and CLKoutY2 are configured as CMOS(Norm/Norm) format 

    3- The skew of CLKoutY1_P and CLKoutY2_P when Y1 and Y2 are configured to LVPECL format 

     

    Regards,

    Sandra Saba 

  • 0 in reply to Sandra Saba
    Prodigy 215 points

    Hi, Sandra:

    Thank you very much.

    But, why is the amplitude about 1.6v based on 500mv vertical scale? The VOH given by spec is Vcc-0.1 (about 3.2v)

    you use 50ohm load to load the SMA on the board, then use probe to access the clock with lvcmos format on the board? Or, use cable to connect the SMA on the board to oscilloscope directly?

    Thanks in advance!

    Best regards!

    Jason

  • 0 in reply to Sandra Saba
    Prodigy 215 points

    Hi, Sandra:

    I check the user guide of LMK0482832 EVM, and think that you should use oscilloscope with 50ohm input(not passive probe with 1Mohm  impedance). So 3.3v amplitude of LVCMOS signal is voltage divided to the half because of 50ohm load. 

    Thanks a lot!

    Best regards!

    Jason

  • +1 in reply to shen jie
    TI__Genius 10975 points

    Jason,

    Sandra is OoO and will be back next week. Regardless, the waveforms she sent now with half the swing or he ones she sent before at higher frequencies should result in very similar delays. Hope this answers your question!

    Best,

    Andrea