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ADS1220: Application support

Murdock Taylor
Prodigy 100 points
Part Number: ADS1220
Other Parts Discussed in Thread: MSPM0L1106, , ADS1248, ADS1148, ADS1260, ADS124S06, MSPM0L1306, TPSM365R15

The application is to measure wire resistance from 0 to 2200 ohms with a sub-milliohm resolution in order to calculate the wire length.   The ADS1220 is configured to measure the resistance ratiometrically.  The supply voltage is 3.3VDC (+/- 5%) for DVDD and AVDD.  The measurement is single sided from 0V to Vref.  Vref is generated using a precision 2.000k (0.01%, 5ppm, 1/10W) resistor where IDAC1 (excitation current source) is set for 500uA and outputs at REFP0.  The 2.000k resistor is between REFP0 and REFN0 and this generates Vref = REFP0 - REFN0.  2.000k ohms x 500uA = 1.000V = Vref.  The wire resistance ( 0 to 2200 ohms) is measured between AIN0 and AIN1.  The 500uA flows across the 2.000k resistor and then down the wire connected to AIN0 thru the resistance to be measured (0 to 2200 ohms) and back to AIN1 and then to GND (AVSS).  The ADS1220 would interface via SPI to a TI MSPM0L1106/1306 running at 1MHz.  The ADS1220 would run in Duty-Cycle Mode at 5 SPS (to get the maximum 50/60 Hz filtering and lowest noise result).  The DRDY signal would be used to let the uC know when to read new data.  The ADS1220 is the only item on the SPI bus, so the CS line on the ADS1220 will just be tied to GND.  The MSPM0L1106/1306 uC would do a running average of 4 ADC samples as some additional filtering.  This circuit is very similar to the TI TechNotes SBBAA235A -- "Low-Cost, Single-Chip, Differential Temperature Measurement Solution Using Precision Delta-Sigma ADCs".  The ADS1220 PGA is not used (gain is 1).  This circuit appears to meet the common-mode requirement and the max voltage limit for the IDAC output.

 

                                                                                 3.3VDC       3.3VDC

                                                                                       ^                  ^

                                                                                       |                   |

                                                       -----------------------------------------------

                                          REFP0 |                            DVDD         AVDD

                                -------------------| +   <--- IDAC1 (500uA)

                                |                      |  (Vref+)

                                \                      |

                 Rref =     /                      |     Vref = 2.000k x 500uA = 1.000VDC

                 2.000k    \                      |

                               |         REFP1  |   (Vref-)

                               |-------------------|  

                               |                       |                              ADS1220

                               |             AIN0  |

              ----------------------------------|

              |        Rmeas =                 |

              \     0 – 2200 ohms           |

              /     measurement             |

              \   (milliohm resolution)     |

              |                              AIN1  |

              ----------------------------------|                             DVSS          AVSS

                               |                       -------------------------------------------------

                               v (GND)                                             |                   |

                                                                                        v (GND)       v (GND)

 

The sketch does not show the filter R's and C's on REFN0 and on AIN0 and AIN1.

Question 1 -- Does this circuit look to be viable?

Question 2 -- With a 3.3VDC (AVDD) supply and the ratiometric approach to generating an external Vref, is this as close to the maximum resolution we get and still not violate the IDAC max voltage requirements and the common mode requirements?  (1.000k, 2.000k, and 4.990k are the only available in stock 0.01%, 5ppm, 1/10W, 0605 resistors available to choose from.)

Question 3 -- The data output is in 2's compliment.  In this application would the data need to be converted so the max negative 2's compliment value would equal 0 and smallest value in 2's compliment would equal the max ADC reading equivalent to 1.000VDC?  What is the maximum resolution available for a single ended measurement -- 2^23 rather than 2^24?

Question 4 -- In some application notes such as "RTD Ratiometric Measurements and Filtering Using the ADS1148 and ADS1248 Family of Devices" -- SBAA201A, the above circuit is shown where the IDAC1 current output is on another output pin and the current travels to the measurement circuit (AIN0, to the 0 - 2200 ohms to be measured, AIN1) and then to the precision resistor (2.000k) connected to REFP0 and REFN0 and then to GND.  Can the ADS1220 be configured for this type of circuit?  If so, what advantages/disadvantages does it have other than the measurement data in 2's compliment is now single sided and positive?

  • 0
    TI__Guru** 113765 points

    Hi Murdock,

    This method is very similar to a ratiometric RTD measurement.  For additional information see A Basic Guide to RTD Measurements.  What you are proposing is a 2-wire measurement with high-side reference.  One error you may see is related to the length of the connection from your board to the wire.  Follow the information in the basic guide for 2-wire RTD with low-side reference.

    I would suggest you use the low-side reference instead of the high-side.  Using a low-side reference allows you to use the PGA for higher input impedance.  You need to have a reference resistor value greater than resistance you are measuring (or at the very least the same value).  Also, you gain nothing by using duty-cycle mode.  Duty-cycle mode takes one 20sps conversion and sits idle for three 20sps conversion periods.  So you will see no noise improvements using this mode.  Averaging should help with the noise.

    Murdock Taylor said:
    Question 1 -- Does this circuit look to be viable?

    The circuit concept if viable, but I think the noise will make it difficult.  The ADC converter will have 13.67uVpp noise.  If my rough calculation is correct this will get you to about 13mOhms resolution noise-free without averaging.  You may want to consider a lower noise ADC such as the ADS124S06 or the ADS1260.  Sub-milliOhm is rather ambitious.

    Murdock Taylor said:
    Question 2 -- With a 3.3VDC (AVDD) supply and the ratiometric approach to generating an external Vref, is this as close to the maximum resolution we get and still not violate the IDAC max voltage requirements and the common mode requirements?  (1.000k, 2.000k, and 4.990k are the only available in stock 0.01%, 5ppm, 1/10W, 0605 resistors available to choose from.)

    IDAC compliance is AVDD-0.9V, so as long as your total voltage drop from the IDAC output pin to ground is 2.4V or less you should be ok.  Using the low-side reference removes the common-mode restriction.

    Murdock Taylor said:
    Question 3 -- The data output is in 2's compliment.  In this application would the data need to be converted so the max negative 2's compliment value would equal 0 and smallest value in 2's compliment would equal the max ADC reading equivalent to 1.000VDC?  What is the maximum resolution available for a single ended measurement -- 2^23 rather than 2^24?

    For this circuit you will only see positive codes (0h to 7FFFFFh) for the measurement range.  However it is possible that there could be a negative offset from the ADC in which case near 0 you may see negative codes.  But to answer the question your measurement range is 2^23 bits.  That is the resolution of the ADC but not the resolution of your measurement because of noise.  The ADC noise is about 13.67uV which is about 7 bits of noise and your measurement resolution is about 17 bits.  If your reference resistor is 2200 then the measurement resolution is 2200/2^17.

    Murdock Taylor said:
    Question 4 -- In some application notes such as "RTD Ratiometric Measurements and Filtering Using the ADS1148 and ADS1248 Family of Devices" -- SBAA201A, the above circuit is shown where the IDAC1 current output is on another output pin and the current travels to the measurement circuit (AIN0, to the 0 - 2200 ohms to be measured, AIN1) and then to the precision resistor (2.000k) connected to REFP0 and REFN0 and then to GND.  Can the ADS1220 be configured for this type of circuit?  If so, what advantages/disadvantages does it have other than the measurement data in 2's compliment is now single sided and positive?

    I think I have already covered this one.  I would recommend using the low-side reference for the reasons I stated above.  Regardless of the reference location the measurement is always the same and the output is binary 2's complement.  As the current is only flowing in a single direction, AINP will always be greater in voltage value than AINN which results in positive output codes only.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Prodigy 100 points

    Additional questions for TI E2E forum for ADS1220:

     

    Thanks for your help.  I looked in “A Basic Guide to RTD Measurements” at the 2 wire RTD measurement circuit with a low side reference (Figure 2-1 on page 10) and I have a few questions.  If the proposed circuit has the IDAC1 output (500uA) going out of AIN0 and to Terminal1 going out to the wire to be measured (0 ohms to 2000 ohms).  The return from the wire to be measured comes back to Terminal2.  The resistance measurement is across Terminal1 and Terminal2 with the signal on Terminal1 going to AIN1 and the signal on Terminal2 going to AIN2.  Terminal2 goes to one side of the reference resistor (2.000k, 0.01%, 5ppm) with the other side of the reference resistor going to AGND.  The signal across the reference resistor goes to REFP0 and REFN0.

     

    The circuit diagram shows an input resistor on AIN1, and input resistor on AIN2, with capacitors from AIN1 to AGND, AIN2 to AGND, and between AIN1 and AIN2.  The same resistor/capacitor network is shown on REFP0 and REFN0.

     

    In this application the 2-wire measurement approach looks to be what I am looking for.  Since the resistance to be measured is the resistance of the wire itself, it is different from measuring a remote RTD whose wires you do not want to include in the measurement.  The wire to be measured is a special twisted pair connected between Terminal1 and Terminal2 on the PCB, and can measure from a short across the terminals to around 1k.  The end of the twisted pair has a 1k termination resistor across the wires.  The twisted pair wire has a wire resistance of so many milliohms per foot.  During an event, the twisted pair wire is shorted somewhere along its length.  The ADS1220 circuit needs to measure the resistance of the shorted wire and calculate the length from the Terminals to the short in the twisted pair wire.  The short is just between the wires in the twisted pair and NOT a short to GND or any other voltage.  The twisted pair wire can be from several hundred feet up to 10,000 feet in length. 

     

    The system is powered from 24VDC.  The 24VDC is stepped down to 5VDC using a TI TPSM365R15 buck converter.  An LDO drops the 5VDC to 3.3VDC to power the low power microcontroller (TI MSPM0L1306/1106 ARM Cortex M0+) running at 1MHz.  The uC talks to the ADS1220 via SPI with the DRDY line used to let the uC know when data is ready.  The ADS1220 will sample continuously at 20 SPS.  The uC will do a rolling average of 16 samples to produce an averaged value to use.  The uC also interfaces to 3 momentary push buttons and a 2-line x 20-character display via I2C.  The uC, ADS1220, and the character display all operate from the 3.3VDC.  The expected current on the 3.3VDC LDO is less than 10mA and probably typically 2-3mA.  The DVDD and AVDD for the ADS1220 is the same 3.3VDC LDO output.

     

    Question 1 -- What happens to the 2-wire RTD measurement circuit with a low side reference as the resistance to be measured approaches and/or exceeds the value of the reference resistance?  Will the ADS1220 just read full scale (7FFFFFh)?  Will the ADS1220 be damaged?  Will the ADS1220 recover as soon as the resistance to be measured drops below the reference resistor?

     

    Question 2 – If there is a break in the wire to be measured (open circuit across the terminals), what would the ADS1220 read?  Is there a way to detect on open circuit?

     

    Question 3 -- What are recommended values for the resistors and capacitors in the noise filtering networks for AIN1 and AIN2 as well as for REFP0 and REFN0?

     

    Question 4 – What RC filtering would you recommend between the DVDD and AVDD at the ADS1220?  What bypass capacitors would you recommend on the ADS1220?

     

    Question 5 – AVSS and DVSS can be two separate ground planes that are only connected at one point.  (Note: The analog ground plane is used exclusively by the ADS1220.)  Normally, I would connect analog GND and digital GND at the 3.3VDC LDO as a star ground, but is there a better place to connect the two ground planes (AVSS & DVSS) such as at the ADS1220?

  • 0 in reply to Murdock Taylor
    TI__Guru** 113765 points

    Hi Murdock,

    Murdock Taylor said:
    Question 1 -- What happens to the 2-wire RTD measurement circuit with a low side reference as the resistance to be measured approaches and/or exceeds the value of the reference resistance?  Will the ADS1220 just read full scale (7FFFFFh)?  Will the ADS1220 be damaged?  Will the ADS1220 recover as soon as the resistance to be measured drops below the reference resistor?

    If the measurement exceeds the reference resistor you will see positive full-scale (7FFFFFh).  This will not damage the ADC.  The ADC will recover following any analog settling at the input.  If the total resistance causes the an invalid condition for IDAC compliance, then there will be both analog settling at the ADC inputs and the reference inputs which can take some time to fully recover.  Again, the conversion is invalid but the input voltages are not exceeding the ratings for the device.

    Murdock Taylor said:
    Question 2 – If there is a break in the wire to be measured (open circuit across the terminals), what would the ADS1220 read?  Is there a way to detect on open circuit?

    The reference will now become '0' and you will see a full-scale reading.

    Murdock Taylor said:
    Question 3 -- What are recommended values for the resistors and capacitors in the noise filtering networks for AIN1 and AIN2 as well as for REFP0 and REFN0?

    The input filter has two purposes.  One is as an antialiasing filter and the second is to provide additional filter from external noise.  Your circuit design is adding a big and long wire antenna.  Twisted wire will  reduce common-mode noise pickup, but where the wire connects to the external 1k resistor and to the PCB there may be some noise pickup at the connection points.  I would suggest following the datasheet information in section 9.1.2.  In this section it is stated that "using a first-order RC filter with a cutoff frequency set at the output data rate or 10x higher is generally a good starting point for a system design."

    Murdock Taylor said:
    Question 4 – What RC filtering would you recommend between the DVDD and AVDD at the ADS1220?  What bypass capacitors would you recommend on the ADS1220?

    Ferrites and inductances are not recommended.  Using an RC filter is ok as long as the resistance values are small (1-2 Ohm range).  Generally we recommend 100nF bypass capacitors.  I have also used 1uF caps if they are MLCC X7R where the inductance is low.

    Murdock Taylor said:
    Question 5 – AVSS and DVSS can be two separate ground planes that are only connected at one point.  (Note: The analog ground plane is used exclusively by the ADS1220.)  Normally, I would connect analog GND and digital GND at the 3.3VDC LDO as a star ground, but is there a better place to connect the two ground planes (AVSS & DVSS) such as at the ADS1220?

    You can use a star ground if the connections a very low impedance.  The ADS1220 requires a low impedance connection between AGND and DGND with unipolar supplies.  You can use a single ground and most of the time that is how the EVMs are designed.  The key point is to make sure digital currents from signal traces, clock, etc., do not flow across the analog portion.  You could also make a 0 Ohm connection between grounds very close to the ADS1220.

    One other thought and that is even though the average current of devices may be well within a small current, the transient currents from switching can be quite large (20-30mA peak current or more). So make sure that the LDO chosen for 3.3V has enough capacity.  I would suggest targeting 100mA output minimum for the LDO.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Prodigy 100 points

    Bob:

    In your answer to Question 1 above "If the measurement exceeds the reference resistor you will see positive full-scale (7FFFFFh).  This will not damage the ADC.  The ADC will recover following any analog settling at the input.  If the total resistance causes the an invalid condition for IDAC compliance, then there will be both analog settling at the ADC inputs and the reference inputs which can take some time to fully recover.  Again, the conversion is invalid but the input voltages are not exceeding the ratings for the device." 

    Question 1 -- How long would it take for the analog settling at the ADC inputs and reference inputs -- typically?  How long would it take for the invalid condition on IDAC compliance to recover?  The signal I am measuring is essentially static where it will be 7FFFFFh most of the time (99.999%) and only rarely make a step change to a measurable value within the expected measurement range.  As long as the ADS1220 can recover to make accurate measurements within a second or so it is no problem.  If it will take longer (i.e. 5 sec to 1 min), it can be accommodated but the system would have to take this into account.

    Question 2 -- With the input terminals shorted at the PCB with the ADS1220, the measured result should be very close to 700000h (7000xxh).  You indicated that the results in this circuit should be positive between 700000h to 7FFFFFh.  You also said that it may be possible that the results around 0 may jump up and down from positive to negative.  If the ADS1220 is set for 20 SPS and a running average is done using the last 16 results, what problems would you see if any measured value of 8xxxxxh is just discarded and 700000h is used in its place?

    Question 3 -- This question is about the RC noise filtering on the analog inputs and the reference inputs.  I understand that for the best antialiasing, the filter cutoff should be around 200Hz for 20 SPS sampling.   If the sampling is 20 SPS and the measured value is fixed (essentially like DC), do you have any recommended R & C values to use -- input resistors, capacitors to GND on the inputs, and capacitor across the inputs?  Should I assume that the RC noise filtering on the analog inputs would be the same on the reference inputs?  

    Thanks.

    Murdock

  • 0 in reply to Murdock Taylor
    TI__Guru** 113765 points

    Hi Murdock,

    I apologize for the delayed response.

    Murdock Taylor said:
    Question 1 -- How long would it take for the analog settling at the ADC inputs and reference inputs -- typically?  How long would it take for the invalid condition on IDAC compliance to recover?  The signal I am measuring is essentially static where it will be 7FFFFFh most of the time (99.999%) and only rarely make a step change to a measurable value within the expected measurement range.  As long as the ADS1220 can recover to make accurate measurements within a second or so it is no problem.  If it will take longer (i.e. 5 sec to 1 min), it can be accommodated but the system would have to take this into account.

    Unfortunately I can't give you a specific answer because there are too many unknowns.  Basically what is happening is you are charging the input filter capacitors to a specific value and then the only place for the excess charge to flow is back out through the input filters to the rest of the circuit.  You can try creating a simulation of your input circuitry to determine a baseline response.

    Murdock Taylor said:
    Question 2 -- With the input terminals shorted at the PCB with the ADS1220, the measured result should be very close to 700000h (7000xxh).  You indicated that the results in this circuit should be positive between 700000h to 7FFFFFh.  You also said that it may be possible that the results around 0 may jump up and down from positive to negative.  If the ADS1220 is set for 20 SPS and a running average is done using the last 16 results, what problems would you see if any measured value of 8xxxxxh is just discarded and 700000h is used in its place?

    Here there may be some misunderstanding.  The ADS1220 output is always binary 2's complement.  Positive codes are from 0h to 7FFFFFh.  Negative codes are from FFFFFFh (-1) to 800000h (-8388607).  If you short the inputs you may see a slight negative offset.

    Murdock Taylor said:
    Question 3 -- This question is about the RC noise filtering on the analog inputs and the reference inputs.  I understand that for the best antialiasing, the filter cutoff should be around 200Hz for 20 SPS sampling.   If the sampling is 20 SPS and the measured value is fixed (essentially like DC), do you have any recommended R & C values to use -- input resistors, capacitors to GND on the inputs, and capacitor across the inputs?  Should I assume that the RC noise filtering on the analog inputs would be the same on the reference inputs?  

    In my response to question 1, there will be analog settling based on the analog input filters.  As your use case is not one that I have used or tested it is difficult for me to determine or recommend values.  You could initially try 2.7k for the resistors, 100nF for the differential cap and 10nF for the common-mode capacitors.  The filtering for the reference would be designed similarly.

    Best regards,

    Bob B