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ADS1262: ADC channel is not getting calibrated when manually adding value to calibration registers

Prakash B B
Prodigy 140 points
Part Number: ADS1262

Hi,

I am working on ADS1262 ADC interfaced to FPGA (XC7A75TFGG676-2L). The control registers are programmed as:

POWER_REG= 0x01, INTERFACE_REG=0x00, MODE0_REG= 0x00, MODE1_REG=0x60, MODE2_REG=0x0B, MUX_REG=0x12. And ADC clock = 7.3728 MHz from generated from FPGA.

After RESET_CMD (/CS enabled already) and waiting for sufficient amount of time (8 ADC clock cycles), I am sending the write command (24-bit) for writing the registers individually. After MUX_REG write I am setting START signal to 1 (not disabled after that) and waiting for /DRDY low pulse. Once after that I am reading (using READ_DIRECT method) the 32-bit by sending SCLK clock (=ADC clock/8 ~1MHz) pulses after every /DRDY low pulse. I am able to read the data output but I have 2 queries:

1. The noise free bits are 15 rather 18+. Why?

2. I am trying to calibrate by writing 24-bit value using write command (by sending 40 SCLK clock pulses (CMD + start_reg_addr + num_reg + calib_value = 3 + 5 + 8 + 24 = 40)) to calibration register, but ADC output is driven high not pulsating at all after write. Why?

Calibration procedure: Evaluate the 24-bit value, write to the register after reading 32-bit output and wait for /DRDY to go high and then wait for /DRDY low pulse and start reading as mentioned afore. During calibration START=1, /CS=0, SCLK=0.

Any help on finding the issue?

Thanks

  • 0
    TI__Mastermind 46541 points

    Hi Prakash B B,

    Prakash B B said:
    The noise free bits are 15 rather 18+. Why?

    What signal are you measuring? What is your reference voltage, gain, and data rate?

    Prakash B B said:
    . I am trying to calibrate by writing 24-bit value using write command (by sending 40 SCLK clock pulses (CMD + start_reg_addr + num_reg + calib_value = 3 + 5 + 8 + 24 = 40)) to calibration register, but ADC output is driven high not pulsating at all after write. Why?

    It would be helpful to see the communication with a logic analyzer so we can better understand what information you are sending to the ADC and how the ADC responds. Please include all relevant signals (CS, DOUT, DIN, SCLK, DRDY)

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 140 points

    Hi Bryan,

    Thanks for the response.

    Open circuit signal is being measured. Internal reference voltage i.e., 2.5V, gain = 1, and data rate = 4800.

    I am attaching the screenshots as below. I couldn't capture them all at a time. Read one after the other.

    Regards

    Prakash

  • 0 in reply to Prakash B B
    TI__Mastermind 46541 points

    Hi Prakash B B,

    What do you mean by "open circuit signal is being measured"? Are you saying that your inputs are just floating? If so, that is why you are getting worse performance than expected. You need to apply a full-scale signal to get the best effective resolution possible

    Can you please label the screenshots so I know what I am looking at? I don't understand what this information is showing, you have dozens and dozens of SCLKs so this is clearly not just one command you are sending

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 140 points

    Hi Bryan,

    Yes, I tried reading the floating inputs as well as input shorted. For both the resolution is not as per datasheet. After that I connected COD sensor, then also the resolution is not as per the datasheet.

    I have highlighted the state transition in below screenshots.

    I feel you can read it now and make out the read/write commands.

    Regards

    Prakash

  • 0 in reply to Prakash B B
    TI__Mastermind 46541 points

    Hi Prakash B B,

    Thanks for providing the annotated scope shots, this helps.

    How are you intending to calibrate? Is this your process?

    • Manually shorting the ADC inputs together using the INPMUX register
    • Take a (32-bit) data measurement that represents the ADC offset
    • Right shift this 32-bit value in your controller to get a 24-bit value
    • Write this 24-bit value back to the OFCALx registers using the RREG command

    So what is your issue? I did not see a SFOCAL1 command in the logic analyzer shots you mentioned, so I am not sure why you are waiting for DRDY

    What noise values are you getting? Can you share a list of ADC output codes you receive during the input short test in order to perform the noise calculations?

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 140 points

    Hi Bryan,

    Yes, I have calculated the value and written to OFCALx register. The problem was I was unable to write the data to register. Now I sorted out. It was the write operation which has additional clock cycles than the required. Since it's real time observation I just gave calibration command in between after reading the channel data. So, it seems to be I am waiting for DRDY which is for previous channel data.

    In the given snaps no command for SFOCAL1. I had captured for offset calibration alone.

    Noise values it's difficult to share it as I can't copy the data from FPGA. Let me check if possible will share with you.

    Regards

    Prakash

  • 0 in reply to Prakash B B
    TI__Mastermind 46541 points

    Hi Prakash B B,

    Thanks for the update, I will wait to see if you can provide the noise data

    -Bryan