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ADS125H01: Relationship between external clk and sampling rate

Shinichi Inoue
Guru 20351 points
Part Number: ADS125H01

Tool/software:

Dear Specialists,

My customer is considering ADS125H01 and has a question about relationship between external clock and sampling rate.

I would be grateful if you could advise.

---

I want to input a 6.144MHz external clock signal to the ADS125H01 and output 2400sps.

Is it possible to achieve this by setting bits 7:3 DR[4:0]DR of the Mode 0 (MODE0) Register (address = 02h) to 01010?

Is this understanding correct?

Or is it necessary to set the external clock frequency to 7.328MHz for outputting 2400SPS?

ｰｰｰ

I appreciate your great help in advance.

Best regards,

Shinichi

  • +1
    TI__Mastermind 40891 points

    Hi Shinichi Inoue,

    Shinichi Inoue said:
    Or is it necessary to set the external clock frequency to 7.328MHz for outputting 2400SPS?

    Yes this is correct. The data rates will scale with the clock frequency. If you provide a 6.144 MHZ clock, then the data rate will scale by a factor of 6.144 / 7.3728 = 0.83333

    Therefore, the 2400 SPS data rate will actually be 2000 SPS

    -Bryan

  • 0 in reply to Bryan Lizon86
    Guru 20351 points

    HI Bryan,

    Thank you for your reply.

    I understand when 6.144MHz CLK and set 2400SPS, it outputs 2000SPS.

    Because 2400SPS is internal clock (7.3728MHz), it must be scaled  by 6.144/7.3728.

    I'll share the information with the customer.

    I appreciate your great help and cooperation.

    Best regards,

    Shinichi