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comprehension question: Sampling-Rate vs. Settlingtime

Gregor Hadasch
Prodigy 20 points

Hi there,

Im confused reading about the Decimation Filter, included in different 24-Bit Sigma Delta ADCs.

For example the ADS129x datasheet (SBAS459K –JANUARY 2010–REVISED AUGUST 2015) tells me, if I set the DR-Register to any value, for example DR=000 (seen on page 51), the SETTLING TIME(tclkPERIODS) is 296 * tclk(@2,048MHz) = 14,45ms @ HR-Mode. But Table18 on page 67 shows DR=000 means a outputdata rate 32kSPS @HR-Mode.

32kSPS = 0,31ms between two samples!?!

When I want to use this ADC in a ISR for a standard feedback-control, how could match  the SETTLING Time with the Sample Rate?

  • 0
    TI__Mastermind 38745 points
    Hey Gregor,

    The ADC will wait a little over 4 sample periods following the decoding of the START command or receiving the START pin. For 32 kSPS, 4 sample periods is

    4/32kHz = 0.125 ms

    and the item in table 12 indicates that it will take

    296/2.048 MHz = 0.145 ms which is only 20 us greater than 4*t_conversion.

    However, when there is a step change in the input, it will only take 3 conversion periods to settle. That is to say the digital filter is an FIR filter with enough taps for 3 conversion cycles, no matter what the data rate.

    Regards,
    Brian Pisani
  • 0 in reply to Brian Pisani
    Prodigy 20 points

    Ok, so far its ok, a FIR tooks time for conversion, thats right.

    I understand, that the filtered data is ready after 4 times conversion.

    So, it is possible to toggle the start pin with 32 kHz? For example:

    We use the TMS320C28335 DSP and route the R/W Signal to start-pin of the ADC. Do I receive the the continous data after fourth conversion in continous-mode? And what happens with the second or third conversion?

    Im confused about this statement: "Issue a START command or toggle the START pin high to reset the digital filter, effectively dropping the data
    rate by a factor of four." on page 54, [9.4.1.4   Single-Shot Mode]

    As far i understand this, this means the maximum conversion is by 32kSPS/4 = 8kSPS!?!

  • 0 in reply to Gregor Hadasch
    TI__Mastermind 38745 points
    Hey Gregor,

    I think there is confusion about how this device is to be used. I recommend not toggling START at all. Just pull START high during your initialization routine and configure the data rate to be 32 kSPS then the device will output a DRDY signal every 1/32kHz = 31.25 us. Finally, place the device in RDATAC mode which will make it so the data shifts out automatically with SCLK. When your DSP receives a DRDY signal, you can retrieve the data from the device and then wait until the next DRDY signal.

    Regards,
    Brian Pisani