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DAC9881 issue

Harisankar Aravindakshan
Prodigy 140 points
Other Parts Discussed in Thread: DAC9881

Hi,

I am using DAC9881 with the following configuration :-

1) Gain = 0

2) Unsigned binary input mode

3) Standalone mode

4) VREFH = 4.75V

5) VREFL = -0.1V

I am using Kelvin connections for the reference input as recommended in the datasheet.

6) DAC output is connected to the non inverting input of a source follower.

 

Issue : -

- With input code all zeroes (00000h), I am getting 10mV at DAC VOUT.

- The output doesnt change as I increment the digital data, until it reaches abt 5500 codes ( 10mV at DAC VOUT ideally corresponds to abt 5500 codes from zero in the dac register)

- From abt 5500 codes, the output starts responding with incrementing input digital data, and I am able to reach VREFH ( 4.75v ) when I give all ones to the DAC

- With Gain pin set to high, the DACOUT voltage with all zeroes digital input drops to 7mV ( but the same thing happens here, it doesnt respond till some code and then it starts working fine)

 

Checks done : -

1) Checked the timing of CS, SCLK, SDATA, LDAC - they are fine

2) Checked the data which is coming out of SDOUT, its giving out the previous data, and its correct, (I checked for codes starting from 00000h to 00002h and they are all correct) which means data latched into the input shift register is correct

 

Please help in debugging this issue

 

Regards,

Harisankar A

 

 

 

 

 

  • 0
    TI__Mastermind 43915 points

    Hi Harisankar, 

    The 10mV is the headroom from the rails required to power the DAC's internal op amp. A lot of DACs will have a built in amplifier so the DAC is capable of driving any kind of load. The built in amplifier's output will have some headroom from the power rails. This is different than the "offset error" of the DAC. 

    Regards,

    Tony Calabria 

  • 0 in reply to Tony Calabria
    Prodigy 140 points

    Hi Tony,

    first of all, i didnt see any headroom specification mentioned in the specsheet. If its headroom, then why its mentioned in the specsheet that VREFL can be as low as -0.2V? 

    Also then, the equation 1 will not hold true right?  (since the output will be masked by this 10mV)

     

    Regards,

    Harisankar A

  • 0 in reply to Harisankar Aravindakshan
    TI__Mastermind 43915 points

    Hi Harisankar, 

    The spec for VREFL allows it to be within +/-0.2V from ground. This is in place because there is an internal diode restricting VREFL to be within a certain limit from ground. One thing that you can do is set VREFL by about 10+mV to minimize the effect of the internal op amp headroom on the output codes. 

    Equation 1 does hold true. You will notice if VREFL is tied to ground and the first few codes will cause the output to stay somewhere around 10mV and not respond. Internally, the R2R resistor string is changing, however the output is limited due to the internal op amp. The equation will hold true as soon as the input code corresponds to a value greater than the headroom required for the output amplifier. The other option is to set VREFL to >+10mV and you will avoid the headroom issues near ground.  

    Regards,

    Tony Calabria