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TCAN4550-Q1: Schematic review

Part Number: TCAN4550-Q1

Hi Team,

There is a good new that DIN TCAN4550RGYRQ1

1. I want to confirm with you, what is the maximum input current of TCAN4550RGYRQ1 under normal operation? I want to confirm the specifications of the LDO from my side

2, Please help check this SCH, THX

  • Kygo,

    I have assigned this thread to an expert and they will be responding accordingly.

    Regards,

    Eric Hackett 

  • Hi Kygo,

    1. I want to confirm with you, what is the maximum input current of TCAN4550RGYRQ1 under normal operation? I want to confirm the specifications of the LDO from my side

    The datasheet lists the maximum supply current for different modes and conditions in the Isup parameter in Supply Characteristics table of the datasheet.  The maximum normal mode supply current during a Dominant bit with a normal bus load (RL = 60 ohms) is 80mA.  WIth a maximum bus load of RL = 50 ohms, the maximum current is 90mA.  Both of these specs are without a load on the VCCOUT.  If the VCCOUT LDO is used, this current would need to be added to the Isup current. 

    I'm not sure what specifications you need clarified.  The internal LDO supplies the 5V for the integrated CAN transceiver and can source up to 70mA of additional current for an external load such as a MCU.  The LDO specifications are listed in the VCCOUT Supply Terminal section of the Electrical Characteristics table in the datasheet.  If there is a specific question please let me know.

    2, Please help check this SCH, THX

    The schematic looks good.  However I would strongly recommend that a series resistor be added between the OSC1 pin and the Crystal.  This is commonly referred to as a series dampening resistor and it will help in optimizing the circuit to achieve the best performance.  The TCAN4550-Q1 supports both a crystal and a single-ended clock. 

    As described in the datasheet, when a single-ended clock is used, the OSC2 pin should be grounded so that the device can detect a "low voltage" on this pin and disable the Pierce Oscillator Amplifier so that it does not conflict with the input clock.  If the Crystal and Load Capacitors are not properly balanced and optimized, the voltage levels of the oscillation waveform on the OSC2 side of the crystal can vary in size and potentially drop below the single-ended clock detection threshold and disable the amplifier.

    The series dampening resistor can help regulate the voltage level and reduce the current through the crystal allowing optimal cap values and lower drive levels.

    I suggest adding a 0-ohm resistor for now that can be replaced with a more appropriate value later if needed.  Every crystal and PCB layout is different and the circuit should evaluated and optimized.  Some applications do not require a resistor, but some do, and we have seen typical values between 50 ohms and 100 ohms suffice.  If this resistor is not included in the design, all adjustments must be made through increasing the cap values, and this can affect the frequency and drive level of the crystal.

    Regards,

    Jonathan