DS90UB941AS-Q1: Symmetric Splitting – Left/Right setting questions

Zirui Su

Part Number: DS90UB941AS-Q1

Hi team

Customer used the 941AS splitter mode but could not output the picture. Besides, they used Independent 2:2 mode and successfully to output the SoC 1920*720 picture and they connected the DSI only with 941AS DSI port0. If they switch the mode to Symmetric Splitting- Left/Right, they monitored the 948 (DES side) output lane 3 and found that there was no Hsync and Vsync waveform, but there was a clock output from 948 which was 1/2 of the DSI clock and this was proper.

Here I listed customer register configuration from 941AS:

unsigned char ds90ub941_reg_init[INIT_MAX_REG][2]=

{

{0x01,0x0c},

{0x56,0x80},

{0x1E,0x01},

{0x32,0xc0},//

{0x33,0x03},//

{0x4f,0x8c},

{0x5b,0x07},

{0x40,0x04},

{0x41,0x05},

{0x42,0x0e},

{0x01,0x00},

};

Could you please help to check when customer would like to use Symmetric Splitting - left/right setting, what configuration should be set to 941AS to successfully output the SoC picture?

over 3 years ago

0 Ben Dattilo over 3 years ago

TI__Mastermind 25765 points

Hi Zirui,

I have a few concerns with this configuration:

Zirui Su said:
{0x01,0x0c},

This command should be split into two different commands, it is good practice to make sure only one bit in this register is written to at a time.
- For example:
  board.WriteI2C(UB941AS,0x01,0x02) # Reset
  
  time.sleep(0.1)
  
  board.WriteI2C(UB941AS,0x01,0x08) # Disable DSI

Zirui Su said:
{0x32,0xc0},//

{0x33,0x03},//

This sets 2D line size to 960. What is the full timing you are using? If the video timing for one display is 1920x720, this 2D line size should be set to 1920, not 960.

Zirui Su said:
{0x40,0x04},

{0x41,0x05},

{0x42,0x0e},

I am doubtful that this is the correct TSKIP value, can you provide full timing including PCLK?

Zirui Su said:
{0x01,0x00},

Before this command there are some missing steps. Typically there is cropping and init commands.
- For example:
  board.WriteI2C(UB941AS,0x1E,0x01) # Select port 0: 1920x720
  
  board.WriteI2C(UB941AS,0x36,0x00)
  
  board.WriteI2C(UB941AS,0x37,0x80) # X Start = 0
  
  board.WriteI2C(UB941AS,0x38,0x7F)
  
  board.WriteI2C(UB941AS,0x39,0x07) # X Stop = 1919
  
  board.WriteI2C(UB941AS,0x3A,0x00)
  
  board.WriteI2C(UB941AS,0x3B,0x00) # Y Start = 0
  
  board.WriteI2C(UB941AS,0x3C,0xCF)
  
  board.WriteI2C(UB941AS,0x3D,0x02) # Y Stop = 719
  
  board.WriteI2C(UB941AS,0x1E,0x02) # Select port 1: 1920x720
  
  board.WriteI2C(UB941AS,0x36,0x00)
  
  board.WriteI2C(UB941AS,0x37,0x80) # X Start = 0
  
  board.WriteI2C(UB941AS,0x38,0x7F)
  
  board.WriteI2C(UB941AS,0x39,0x07) # X Stop = 1919
  
  board.WriteI2C(UB941AS,0x3A,0x00)
  
  board.WriteI2C(UB941AS,0x3B,0x00) # Y Start = 0
  
  board.WriteI2C(UB941AS,0x3C,0xCF)
  
  board.WriteI2C(UB941AS,0x3D,0x02) # Y Stop = 719
  
  board.WriteI2C(UB941AS,0x40,0x10) # Init DSI Clock Settings (From Section 10.2 of datasheet)
  
  board.WriteI2C(UB941AS,0x41,0x86) # Init DSI Clock Settings (From Section 10.2 of datasheet)
  
  board.WriteI2C(UB941AS,0x42,0x0A) # Init DSI Clock Settings (From Section 10.2 of datasheet)
  
  board.WriteI2C(UB941AS,0x41,0x94) # Init DSI Clock Settings (From Section 10.2 of datasheet)
  
  board.WriteI2C(UB941AS,0x42,0x0A) # Init DSI Clock Settings (From Section 10.2 of datasheet)
  
  board.WriteI2C(UB941AS,0x01,0x00) #Release DSI

Regards,

Ben

0 Zirui Su over 3 years ago in reply to Ben Dattilo

TI__Expert 5340 points

Hi Ben,

Sure I will let customer to have a try for these commands. Besides, Customer has requirement of using DSI clock in 941AS splitter mode for 2 different timing specs displays, so please help us to generate the script for us or to check whether the splitter mode could work for these 2 displays:

display A timing:

display B timing:

Here is the topology and signal transport link:

Customer uses single DSI port 0 input for 941AS and splitter mode to output 2 display with above timings. In my opinion splitter mode need the same Htotal*Vtotal right? Please double check how could we implement this solution with your script, thank you.

0 Ben Dattilo over 3 years ago in reply to Zirui Su

TI__Mastermind 25765 points

Hi Zirui,

It is possible for the 941AS to do asymmetric splitting in certain cases. Ideally the vertical dimensions will be the same for the two panels, because in the smaller panel, the excess active video is turned into blanking. In this case, the active video is the same dimension for both the vertical and horizontal, but with different blanking. So it's not exactly an asymmetric split. It would certainly be more straightforward if the two panels had the exact same timing, however it's unclear if that's possible since display B spec doesn't show minimums.

This being said, I am confused about the topology you have posted. It shows the DSI input to the 941 is 3840x720, which is 4x the timing of a single display. In a symmetric split, the superframe should be 2x the timing of a single display. In this case the superframe should be 1920*720. Then this superframe is split over the two ports for two displays with the dimension 960*720.

Regards,

Ben

0 Zirui Su over 3 years ago in reply to Ben Dattilo

TI__Expert 5340 points

Hi Ben

Let me clarify the topology picture. They used one 941AS with 2 ports respectively connected to one 948. Each 948 use dual oldi mode to output a 1920*720 display, so you could see lvds1 and lvds2 respectively drives 960*720. So I think the timing for A and B screen, the H parameters should multiply 2. Do you understand the topology now?

Here is their software configuration to implement the topology, please help to check whether it is right:

941 splitter mode configuration.txt

{0x01,0x0f},
{0x1E,0x01},
{0x4f,0x8c},
{0x5b,0x07},
{0x40,0x05},
{0x41,0x21},
{0x42,0x60},
{0x40,0x04},
{0x41,0x05},
{0x42,0x0e},
{0x32,0x80},//1920
{0x33,0x07},//
{0x66,0x03},
{0x67,0x68},
{0x66,0x1a},
{0x67,0x19},
{0x6a,0x88},
{0x6b,0x10},
{0x6c,0x10},
{0x1E,0x02},
{0x66,0x03},
{0x67,0x68},
{0x66,0x1a},
{0x67,0x19},
{0x6a,0x88},
{0x6b,0x0c},
{0x6c,0x10},
{0x1E,0x01},
{0x56,0x82},
{0x01,0x00},

Besides, if we want to change the clock source from internal ref clk to DSI clk, just config 0x56 register without changing other registers to successfully output?

0 Ben Dattilo over 3 years ago in reply to Zirui Su

TI__Mastermind 25765 points

Hi Zirui,

What you described makes sense, but it does not match the timing you have shown me. The two display timings you previously attached show two displays with 960*720 timing. You described two displays with 1920*720 timing:

Zirui Su said:
Each 948 use dual oldi mode to output a 1920*720 display

So basically I need confirmation on the timing of the two displays being used. If it is indeed two 1920*720 displays, can you provide the timing for those displays? Since the previous timings are not for 1920*720.

There might be a misunderstanding about 2*H. Just to clarify: In a symmetric splitting scenario, the 941AS should receive 2*H timing, and normal V timing. 2D Line width should be programmed to the actual Horizontal Width of the display, not 2*H. The two 948s will each receive the actual timing (not 2*H) and function normally.

Zirui Su said:
Besides, if we want to change the clock source from internal ref clk to DSI clk, just config 0x56 register without changing other registers to successfully output?

This is correct.

Regards,

Ben

0 Zirui Su over 3 years ago in reply to Ben Dattilo

TI__Expert 5340 points

Hi Ben

1. Let me clarify the scenario again. We only have 2 displays: A and B therefore I clarify the topology and each of the screen use 1920*720@60hz resolution.

Here is our configuration for 941AS register which followed your 941AS splitter mode documents chapter 7 instruction to configure the splitter mode:

Splitter.txt

             
#941AS configuration, the left one is register address and the right one is value
             
                 {0x01,0x0f},
                 {0x1E,0x01},
                 {0x4f,0x8c},
                 {0x5b,0x07},
                 {0x56,0x80},

                 {0x40,0x05},
                 {0x41,0x21},
                 {0x42,0x60},//HS,vs signal is active low
                 {0x40,0x04},
                 {0x41,0x05},
                 {0x42,0x40}, //PCLK:192MHZ,PCLK*3=DSI CLK, 576MHZ. TSKIP_CNT=0X20

                 {0x32,0x80}, //Set the line size to 1920
                 {0x33,0x07},//

                 {0x34,0x0c},//delay
                 {0x35,0x00},
                
                 {0x1E,0x02},
                 {0x34,0x0c},//delay 
                 {0x35,0x00},
                
                 {0x40,0x10},
                 {0x41,0x86},
                 {0x42,0x0a},
                 {0x41,0x94},
                 {0x42,0x0a},

                 {0x01,0x00},
               }

Splitter Mode Operations With the DS90Ux941ASQ1.pdf

Following is the timing we set to DSI port 0 from 8155 which is ok with both the A and B displays:

Timing.txt

<VideoMode
    eVideoFormat       = '15'
    uActiveH           = '3840'
    uFrontPorchH       = '126'
    uPulseWidthH       = '64'
    uBackPorchH        = '64'
    bActiveLowH        = '1'
    uActiveV           = '720'
    uFrontPorchV       = '45'
    uPulseWidthV       = '8'
    uBackPorchV        = '8'
    bActiveLowV        = '1'
    uPixelFreqInHz     = '191844840'
    uRefreshRate       = '60'
    bInterlaced        = '0'
    bSupported         = '1'
    uPixelRepeatFactor = '0'
    eAspectRatio       = '2'
    eOpMode            = '1'
    bAudioSupported    = '0'
    ePixelFormatType   = '3'
  ></VideoMode>

The phenomenon is the 2 screens both failed to output the picture from SoC, just black screens.

Dump registers for 941AS after running the splitter configuration when black screens happen:

20211104-941log.txt

wymaddr :1,0
wymaddr :2,0
wymaddr :3,92
wymaddr :4,0
wymaddr :5,0
wymaddr :6,68
wymaddr :7,0
wymaddr :8,0
wymaddr :9,1
wymaddr :a,a2
wymaddr :b,d
wymaddr :c,7
wymaddr :d,30
wymaddr :e,0
wymaddr :f,0
wymaddr :10,0
wymaddr :11,0
wymaddr :12,0
wymaddr :13,8f
wymaddr :14,0
wymaddr :16,fe
wymaddr :17,1e
wymaddr :18,7f
wymaddr :19,7f
wymaddr :1a,1
wymaddr :1b,0
wymaddr :1c,0
wymaddr :1d,0
wymaddr :1e,1
wymaddr :1f,0
wymaddr :20,b
wymaddr :21,0
wymaddr :26,0
wymaddr :2e,a5
wymaddr :2f,5a
wymaddr :30,0
wymaddr :32,80
wymaddr :33,7
wymaddr :34,c
wymaddr :35,0
wymaddr :36,0
wymaddr :37,0
wymaddr :38,0
wymaddr :39,0
wymaddr :3a,0
wymaddr :3b,0
wymaddr :3c,0
wymaddr :3d,0
wymaddr :3e,81
wymaddr :3f,2
wymaddr :4f,8c
wymaddr :50,16
wymaddr :54,2
wymaddr :55,10
wymaddr :56,80
wymaddr :57,2
wymaddr :58,0
wymaddr :59,0
wymaddr :5a,f9
wymaddr :5b,7
wymaddr :5c,7
wymaddr :5d,6
wymaddr :5e,44
wymaddr :5f,60
wymaddr :60,22
wymaddr :61,2
wymaddr :62,0
wymaddr :63,0
wymaddr :64,10
wymaddr :65,0
wymaddr :6a,0
wymaddr :6b,0
wymaddr :6c,0
wymaddr :6d,0
wymaddr :6e,20
wymaddr :6f,0
wymaddr :70,0
wymaddr :71,0
wymaddr :72,0
wymaddr :73,0
wymaddr :74,0
wymaddr :75,0
wymaddr :76,0
wymaddr :77,0
wymaddr :78,0
wymaddr :79,0
wymaddr :7a,0
wymaddr :7b,0
wymaddr :7c,0
wymaddr :7d,0
wymaddr :c2,82
wymaddr :c4,38
wymaddr :c6,0
wymaddr :c7,64
wym r_iicreg0031:0,
wym r_iicreg3263:0,
wym r_iicreg6495:0,
wym r_iicreg961270
wymaddr :1,0
wymaddr :2,0
wymaddr :3,92
wymaddr :4,0
wymaddr :5,0
wymaddr :6,58
wymaddr :7,0
wymaddr :8,0
wymaddr :9,1
wymaddr :a,e5
wymaddr :b,a
wymaddr :c,7
wymaddr :d,30
wymaddr :e,0
wymaddr :f,0
wymaddr :10,0
wymaddr :11,0
wymaddr :12,0
wymaddr :13,8f
wymaddr :14,0
wymaddr :16,fe
wymaddr :17,1e
wymaddr :18,7f
wymaddr :19,7f
wymaddr :1a,1
wymaddr :1b,0
wymaddr :1c,0
wymaddr :1d,0
wymaddr :1e,2
wymaddr :1f,0
wymaddr :20,b
wymaddr :21,0
wymaddr :26,0
wymaddr :2e,a5
wymaddr :2f,5a
wymaddr :30,0
wymaddr :32,80
wymaddr :33,7
wymaddr :34,c
wymaddr :35,0
wymaddr :36,0
wymaddr :37,0
wymaddr :38,0
wymaddr :39,0
wymaddr :3a,0
wymaddr :3b,0
wymaddr :3c,0
wymaddr :3d,0
wymaddr :3e,81
wymaddr :3f,2
wymaddr :4f,8c
wymaddr :50,16
wymaddr :54,2
wymaddr :55,10
wymaddr :56,80
wymaddr :57,2
wymaddr :58,0
wymaddr :59,0
wymaddr :5a,f9
wymaddr :5b,7
wymaddr :5c,7
wymaddr :5d,6
wymaddr :5e,44
wymaddr :5f,60
wymaddr :60,22
wymaddr :61,2
wymaddr :62,0
wymaddr :63,0
wymaddr :64,10
wymaddr :65,0
wymaddr :6a,0
wymaddr :6b,0
wymaddr :6c,0
wymaddr :6d,0
wymaddr :6e,20
wymaddr :6f,0
wymaddr :70,0
wymaddr :71,0
wymaddr :72,0
wymaddr :73,0
wymaddr :74,0
wymaddr :75,0
wymaddr :76,0
wymaddr :77,0
wymaddr :78,0
wymaddr :79,0
wymaddr :7a,0
wymaddr :7b,0
wymaddr :7c,0
wymaddr :7d,0
wymaddr :c2,82
wymaddr :c4,78
wymaddr :c6,0
wymaddr :c7,44
wym r_iicreg0031:0,
wym r_iicreg3263:0,
wym r_iicreg6495:0,
wym r_iicreg961270
wymdsi_ind:1,0
wymdsi_ind:2,0
wymdsi_ind:3,1d
wymdsi_ind:4,14
wymdsi_ind:5,40
wymdsi_ind:6,0
wymdsi_ind:7,0
wymdsi_ind:8,0
wymdsi_ind:f,1f
wymdsi_ind:10,0
wymdsi_ind:11,0
wymdsi_ind:12,0
wymdsi_ind:13,0
wymdsi_ind:14,0
wymdsi_ind:15,0
wymdsi_ind:20,7f
wymdsi_ind:21,60
wymdsi_ind:22,ff
wymdsi_ind:23,7f
wymdsi_ind:28,0
wymdsi_ind:29,0
wymdsi_ind:2a,0
wymdsi_ind:2b,0
wymdsi_ind:2c,0
wymdsi_ind:2d,0
wymdsi_ind:30,0
wymdsi_ind:31,20
wymdsi_ind:32,0
wymdsi_ind:33,4
wymdsi_ind:34,0
wymdsi_ind:35,20
wymdsi_ind:36,0
wymdsi_ind:37,0
wymdsi_ind:38,0
wymdsi_ind:3a,2
wymdsi_ind:3b,3
wym_patt:0,0
wym_patt:1,0
wym_patt:2,0
wym_patt:3,8
wym_patt:4,48
wym_patt:5,53
wym_patt:6,1e
wym_patt:7,20
wym_patt:8,3
wym_patt:9,1e
wym_patt:a,a
wym_patt:b,2
wym_patt:c,a
wym_patt:d,2
wym_patt:e,3
wym_patt:f,1e
wym_patt:10,e
wym_patt:11,21
wym_patt:12,43
wym_patt:13,65
wym_patt:14,87
wym_patt:15,a9
wym_patt:16,cb
wym_patt:17,ed
wym_patt:18,f
wym_patt:19,0
wym_patt:1a,1
#

(Left number is reg address and right one is reg value)

2. However, displays could work in 941AS independent 2:2 mode, here I also listed the configuration we have done:

independent.txt

#Independent2：2 mode could display normally
Independent 2:2 Mode
{0x01,0x08},
{0x1E,0x01},
{0x1E,0x04},
{0x1E,0x01},
{0x03,0x9A},
{0x1E,0x02},
{0x03,0x9A},
{0x1E,0x01},
{0x40,0x05},
{0x41,0x21},
{0x42,0x60},
{0x1E,0x02},
{0x40,0x09},
{0x41,0x21},
{0x42,0x60},
{0x1E,0x01},
{0x5B,0x05},
{0x4F,0x8C},
{0x1E,0x01},
{0x40,0x04},
{0x41,0x05},
{0x42,0x1E},
{0x1E,0x02},
{0x4F,0x8C},
{0x1E,0x01},
{0x40,0x08},
{0x41,0x05},
{0x42,0x14},
{0x01,0x00},

Please help us to check what configuration we wrongly/missing configured quickly, the actual application scenario is:

DSI continuous clock mode, DSI single port0, 941AS splitter mode with two 948s.

Wait for your response and please tell us how to successfully configure the 941AS splitter mode, thank you very much!

0 Ben Dattilo over 3 years ago in reply to Zirui Su

TI__Mastermind 25765 points

Hi Zirui,

Got it, thanks for the clarification. Two displays, both 1920*720p. This will be a symmetric split. I also notice the configuration is different than the original one you posted, this time it does align with 1920*720.

I am mostly concerned with programming {0x01,0x0f} as you should really only program one bit at a time in this register. Try this script:

3840x720 Sym Split Script (1).py

# 3840x720@60 Symmetric Split Example - 2x 1920x720@60

# Video 0 and Video 1 Parameters:
# HACT = 1920
# HFP = 64
# HSYNC = 32
# HBP = 32
# VACT = 720
# VFP = 45
# VSYNC = 8
# VBP = 8
# PCLK = 96MHz 

# DSI Superframe Dimensions:
# HACT = 3840
# HFP = 128
# HSYNC = 64
# HBP = 64
# VACT = 720
# VFP = 45
# VSYNC = 8
# VBP = 8
# PCLK = 192MHz 

# DSI clock = 576MHz
# DSI Lane Speed = 1152Mbps/lane 
# 4 Lanes DSI
# DSI input port 0

import time

UB941AS = 0x18

board.WriteI2C(UB941AS,0x01,0x02) # Reset
time.sleep(0.1)
board.WriteI2C(UB941AS,0x01,0x08) # Disable DSI
board.WriteI2C(UB941AS,0x1E,0x01) # Select port 0

board.WriteI2C(UB941AS,0x4F,0x8C) # 4 Lane Mode continuous clock

board.WriteI2C(UB941AS,0x5B,0x07) # Splitter mode

board.WriteI2C(UB941AS,0x40,0x04) # TSKIP_CNT
board.WriteI2C(UB941AS,0x41,0x05) # TSKIP_CNT
board.WriteI2C(UB941AS,0x42,0x40) # TSKIP_CNT

board.WriteI2C(UB941AS,0x56,0x80) # L/R Pixel Processing
board.WriteI2C(UB941AS,0x32,0x80) # Set 2D Line Size 1920
board.WriteI2C(UB941AS,0x33,0x07) # 

board.WriteI2C(UB941AS,0x1E,0x01) # Select port 0: 1920x720
board.WriteI2C(UB941AS,0x36,0x00)
board.WriteI2C(UB941AS,0x37,0x80) # X Start = 0
board.WriteI2C(UB941AS,0x38,0x7F) 
board.WriteI2C(UB941AS,0x39,0x07) # X Stop = 1919
board.WriteI2C(UB941AS,0x3A,0x00)
board.WriteI2C(UB941AS,0x3B,0x00) # Y Start = 0
board.WriteI2C(UB941AS,0x3C,0xCF)
board.WriteI2C(UB941AS,0x3D,0x02) # Y Stop = 719

board.WriteI2C(UB941AS,0x1E,0x02) # Select port 1: 1920x720
board.WriteI2C(UB941AS,0x36,0x00)
board.WriteI2C(UB941AS,0x37,0x80) # X Start = 0
board.WriteI2C(UB941AS,0x38,0x7F) 
board.WriteI2C(UB941AS,0x39,0x07) # X Stop = 1919
board.WriteI2C(UB941AS,0x3A,0x00)
board.WriteI2C(UB941AS,0x3B,0x00) # Y Start = 0
board.WriteI2C(UB941AS,0x3C,0xCF)
board.WriteI2C(UB941AS,0x3D,0x02) # Y Stop = 719

board.WriteI2C(UB941AS,0x40,0x10) # Init DSI Clock Settings (From Section 10.2 of datasheet)
board.WriteI2C(UB941AS,0x41,0x86) # Init DSI Clock Settings (From Section 10.2 of datasheet)
board.WriteI2C(UB941AS,0x42,0x0A) # Init DSI Clock Settings (From Section 10.2 of datasheet)
board.WriteI2C(UB941AS,0x41,0x94) # Init DSI Clock Settings (From Section 10.2 of datasheet)
board.WriteI2C(UB941AS,0x42,0x0A) # Init DSI Clock Settings (From Section 10.2 of datasheet)

board.WriteI2C(UB941AS,0x01,0x00) #Release DSI

Regards,

Ben

0 Zirui Su over 3 years ago in reply to Ben Dattilo

TI__Expert 5340 points

Hi Ben

Thanks for your support but the script still could not work. Here we also dumped the 941AS registers:

20211105-log1.txt

wymaddr :1,0
wymaddr :2,0
wymaddr :3,92
wymaddr :4,0
wymaddr :5,0
wymaddr :6,68
wymaddr :7,0
wymaddr :8,0
wymaddr :9,1
wymaddr :a,8
wymaddr :b,1
wymaddr :c,7
wymaddr :d,30
wymaddr :e,0
wymaddr :f,0
wymaddr :10,0
wymaddr :11,0
wymaddr :12,0
wymaddr :13,8f
wymaddr :14,0
wymaddr :16,fe
wymaddr :17,1e
wymaddr :18,7f
wymaddr :19,7f
wymaddr :1a,1
wymaddr :1b,0
wymaddr :1c,0
wymaddr :1d,0
wymaddr :1e,1
wymaddr :1f,0
wymaddr :20,b
wymaddr :21,0
wymaddr :26,0
wymaddr :2e,a5
wymaddr :2f,5a
wymaddr :30,0
wymaddr :32,80
wymaddr :33,7
wymaddr :34,c
wymaddr :35,0
wymaddr :36,0
wymaddr :37,80
wymaddr :38,7f
wymaddr :39,7
wymaddr :3a,0
wymaddr :3b,0
wymaddr :3c,cf
wymaddr :3d,2
wymaddr :3e,81
wymaddr :3f,2
wymaddr :4f,8c
wymaddr :50,16
wymaddr :54,2
wymaddr :55,10
wymaddr :56,80
wymaddr :57,2
wymaddr :58,0
wymaddr :59,0
wymaddr :5a,f9
wymaddr :5b,7
wymaddr :5c,7
wymaddr :5d,6
wymaddr :5e,44
wymaddr :5f,60
wymaddr :60,22
wymaddr :61,2
wymaddr :62,0
wymaddr :63,0
wymaddr :64,10
wymaddr :65,0
wymaddr :6a,0
wymaddr :6b,0
wymaddr :6c,0
wymaddr :6d,0
wymaddr :6e,20
wymaddr :6f,0
wymaddr :70,0
wymaddr :71,0
wymaddr :72,0
wymaddr :73,0
wymaddr :74,0
wymaddr :75,0
wymaddr :76,0
wymaddr :77,0
wymaddr :78,0
wymaddr :79,0
wymaddr :7a,0
wymaddr :7b,0
wymaddr :7c,0
wymaddr :7d,0
wymaddr :c2,82
wymaddr :c4,38
wymaddr :c6,0
wymaddr :c7,64
wym r_iicreg0031:0,
wym r_iicreg3263:0,
wym r_iicreg6495:0,
wym r_iicreg961270
wymaddr :1,0
wymaddr :2,0
wymaddr :3,92
wymaddr :4,0
wymaddr :5,0
wymaddr :6,58
wymaddr :7,0
wymaddr :8,0
wymaddr :9,1
wymaddr :a,ca
wymaddr :b,0
wymaddr :c,7
wymaddr :d,30
wymaddr :e,0
wymaddr :f,0
wymaddr :10,0
wymaddr :11,0
wymaddr :12,0
wymaddr :13,8f
wymaddr :14,0
wymaddr :16,fe
wymaddr :17,1e
wymaddr :18,7f
wymaddr :19,7f
wymaddr :1a,1
wymaddr :1b,0
wymaddr :1c,0
wymaddr :1d,0
wymaddr :1e,2
wymaddr :1f,0
wymaddr :20,b
wymaddr :21,0
wymaddr :26,0
wymaddr :2e,a5
wymaddr :2f,5a
wymaddr :30,0
wymaddr :32,80
wymaddr :33,7
wymaddr :34,c
wymaddr :35,0
wymaddr :36,0
wymaddr :37,80
wymaddr :38,7f
wymaddr :39,7
wymaddr :3a,0
wymaddr :3b,0
wymaddr :3c,cf
wymaddr :3d,2
wymaddr :3e,81
wymaddr :3f,2
wymaddr :4f,8c
wymaddr :50,16
wymaddr :54,2
wymaddr :55,10
wymaddr :56,80
wymaddr :57,2
wymaddr :58,0
wymaddr :59,0
wymaddr :5a,f9
wymaddr :5b,7
wymaddr :5c,7
wymaddr :5d,6
wymaddr :5e,44
wymaddr :5f,60
wymaddr :60,22
wymaddr :61,2
wymaddr :62,0
wymaddr :63,0
wymaddr :64,10
wymaddr :65,0
wymaddr :6a,0
wymaddr :6b,0
wymaddr :6c,0
wymaddr :6d,0
wymaddr :6e,20
wymaddr :6f,0
wymaddr :70,0
wymaddr :71,0
wymaddr :72,0
wymaddr :73,0
wymaddr :74,0
wymaddr :75,0
wymaddr :76,0
wymaddr :77,0
wymaddr :78,0
wymaddr :79,0
wymaddr :7a,0
wymaddr :7b,0
wymaddr :7c,0
wymaddr :7d,0
wymaddr :c2,82
wymaddr :c4,78
wymaddr :c6,0
wymaddr :c7,44
wym r_iicreg0031:0,
wym r_iicreg3263:0,
wym r_iicreg6495:0,
wym r_iicreg961270
wymdsi_ind:1,0
wymdsi_ind:2,0
wymdsi_ind:3,1d
wymdsi_ind:4,14
wymdsi_ind:5,40
wymdsi_ind:6,0
wymdsi_ind:7,0
wymdsi_ind:8,0
wymdsi_ind:f,1f
wymdsi_ind:10,0
wymdsi_ind:11,0
wymdsi_ind:12,0
wymdsi_ind:13,0
wymdsi_ind:14,0
wymdsi_ind:15,0
wymdsi_ind:20,7f
wymdsi_ind:21,0
wymdsi_ind:22,ff
wymdsi_ind:23,7f
wymdsi_ind:28,0
wymdsi_ind:29,0
wymdsi_ind:2a,0
wymdsi_ind:2b,0
wymdsi_ind:2c,0
wymdsi_ind:2d,0
wymdsi_ind:30,0
wymdsi_ind:31,20
wymdsi_ind:32,0
wymdsi_ind:33,4
wymdsi_ind:34,0
wymdsi_ind:35,20
wymdsi_ind:36,0
wymdsi_ind:37,0
wymdsi_ind:38,0
wymdsi_ind:3a,2
wymdsi_ind:3b,3
wym_patt:0,0
wym_patt:1,0
wym_patt:2,0
wym_patt:3,8
wym_patt:4,48
wym_patt:5,53
wym_patt:6,1e
wym_patt:7,20
wym_patt:8,3
wym_patt:9,1e
wym_patt:a,a
wym_patt:b,2
wym_patt:c,a
wym_patt:d,2
wym_patt:e,3
wym_patt:f,1e
wym_patt:10,e
wym_patt:11,21
wym_patt:12,43
wym_patt:13,65
wym_patt:14,87
wym_patt:15,a9
wym_patt:16,cb
wym_patt:17,ed
wym_patt:18,f
wym_patt:19,0
wym_patt:1a,1

To provide more reference information, customer used the following configuration to achieve Replicate Mode, both screens can be displayed normally, and the DSI clock is also used.

Here is the Replicate Mode configuration:

Replicate mode.txt

                {0x01,0x0f},
                {0x1E,0x01},
                {0x4f,0x8c},
                {0x5b,0x04},
                {0x56,0x00},

                {0x40,0x05},
                {0x41,0x21},
                {0x42,0x60},
                {0x40,0x04},
                {0x41,0x05},
                {0x42,0x40},

                {0x40,0x10},
                {0x41,0x86},
                {0x42,0x0a},
                {0x41,0x94},
                {0x42,0x0a},
                
                {0x32,0x80},//1920
                {0x33,0x07},//

                {0x34,0x0c},// uHsyncWidth+uHsyncBackPorch
                {0x35,0x00},//
                {0x1E,0x02},
                {0x34,0x0c},// uHsyncWidth+uHsyncBackPorch
                {0x35,0x00},//
                {0x1E,0x01},

                {0x01,0x00},

Under the premise of normal Replicate mode, we do not change anything, only switch to splitter mode (0x5B,0x07), but the black screen happened. We would like to know why and need your quick help since the case is urgent, thank you.

0 Ben Dattilo over 3 years ago in reply to Zirui Su

TI__Mastermind 25765 points

Hi Zirui,

Zirui Su said:
Under the premise of normal Replicate mode, we do not change anything, only switch to splitter mode (0x5B,0x07)

Are you only doing this to switch to splitter mode? There are more configurations that need to be done, as can be seen in the script I sent you. Left/Right 3D processing must be enabled, among other configurations. Please incorporate the necessary configurations into your script. These can be found in the script I provided, or even in the Splitter Mode Operations with the DS90Ux941ASQ1 appnote. Here is a snip from this appnote:

If you add these configurations (corresponding to your timing of course), splitter mode should work.

Also, for proper operation of Left/Right 3D format, the images must have identical video format (lines, pixels, blanking). As discussed before, the pixel clock must be twice the frequency needed for a single image. This means the timing from the DSI input must have 2*(Hactive, Hfront porch, Hback porch, Hsync).

Regards,

Ben

0 Zirui Su over 3 years ago in reply to Ben Dattilo

TI__Expert 5340 points

Hi Ben

Since the case is quite urgent, could you please kindly attend the meeting I have sent invitation to you via e-mail so that we could guide customer to do the splitter configuration? Thank you very much. If you have other convenient time, please let us know (we have 15 hours time difference) so your afternoon or evening maybe OK, please help us to fix the issue, thank you.

0 Ben Dattilo over 3 years ago in reply to Zirui Su

TI__Mastermind 25765 points

Hi Zirui,

As was discussed in our meeting, I will double check the DSI/SOC requirements.

Regards,

Ben

0 Ben Dattilo over 3 years ago in reply to Ben Dattilo

TI__Mastermind 25765 points

Hi Zirui,

Can you confirm the following:

DSI mode (burst mode/non-burst mode with sync events/sync pulses)
H/Vsync polarity needed for the two displays
The two display specs you provided have different blanking parameters. Can you please confirm again that the blanking for each display is exactly the same, and provide the correct spec?
If the timing for both displays correlate with the timing in the display B spec, the DSI timing front porch should be 128, not 126.

Regards,

Ben

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DS90UB941AS-Q1: Symmetric Splitting – Left/Right setting questions