TCAN4550: Sending message using TX Buffer

Hi Kevin,

The Nominal Bit Timing settings look ok.  Also, generally your sequence looks good

You would need to provide your actual MRAM configuration register values and the desired number of the various types of buffer and FIFO elements for me to verify you have good starting addresses for each element type and there are no overlapping sections.

There are some examples in the TCAN45xx Software User's Guide that you could try to replicate. 

Kevin Doe said:

The issue is when I try to send my message using TX Buffer 0, there is nothing on-going on CAN and I see that the message is still pending (by reading TXBRP)

Can you clarify what you mean by "there is nothing on-going on CAN"?  Are you looking at the CANH and CANL signals with a scope and you do not see any activity?

Do you have another CAN node on the bus that will acknowledge the message you are trying to send?  If there is not a second CAN node to acknowledge the message, the message will always stay in the "Pending" status because no other node has acknowledged that it has received the transmitted message.

Regards,

Jonathan

Hello Jonathan,

Thank you for your quick reply. Yes I have a PCAN on the bus that is acquiring CAN message. What I mean by nothing on-going on CAN is that I cannot see any frames using my PCAN.

Here is my MRAM configuration :

XIDFC (0x1088)  :

• FLSEA : 0x0000 (for 0x8000)
• LSE : 0x01 (only 1 filter)

    @0x8000 write : 0x3FFFFFFF

• EFEC : 3b001 (Store in Rx FIFO 0)
• EFID1 : 0x1FFFFFF

     @0x8004 write : 0x80000000

•   EFT : 2b10 (Classic filter)
•   EFID2 : 0x00000000

      Can you confirm this configuration should accept all extended incoming frames ?

XIDM (0x1090) :

• EIDM : 0x1FFFFFF

               What is the difference of setting this register and the method above (MRAM configuration at extended id filter address) ?

RXF0C (0x10A0) :

• F0OM : 0 - FIFO 0 blocking mode
• F0WM : 0
• F0S : 0x04 (4 elements)
• F0SA : 0x0100 (for 0x8100)

RXBC (0x10AC) :

• RBSA : 0x0200 (for 0x8200)

RXESC (0x10BC) :

• RBDS : 0x0 (8 bytes data field)
• F0DS : 0x0 (8 bytes data field)

TXBESC (0x10C8)

• TBDS : 0x0 (8 bytes data field)

TXEFC (0x10F0) :

• EFWM : 0x00
• EFS : 0x04
• EFSA : 0x0300 (for 0x8300)

TXBC (0x10C0) :

• TFQM : 1 (Queue)
• TFQS : 4 Tx buffers
• NDTB : 0
• TBSA : 0x0400 (for 0x8400)

I don’t think any overlap is possible with this config.

Thank you,

Kevin

Hi Kevin,

Kevin Doe said:

Can you confirm this configuration should accept all extended incoming frames ?

It looks like you want to accept all messages with ID's between 0x00000000 and 0x1FFFFFF.  Is that correct?  If so I think you would want to use a Range Filter instead of the Classic Filter because the Classic Filter will do a logic AND with the ID and Mask to check each bit for a matching value.  Therefore the classic filter is typically used to single out a specific message ID.

If you want to accept all frames, you can also simply set the Accept Non-Matching Frames Standard/Extended register fields in the Global Filter Configuration (GFC register 0x1080) to accept the frames into either the RX FIFO 0 or RX FIFO 1.

Kevin Doe said:

 What is the difference of setting this register and the method above (MRAM configuration at extended id filter address) ?

The EFID2 field had different meanings depending on how the EFEC field is configured.  The TCAN4550-Q1 uses the MCAN IP developed by Bosch.  Additional information on the MCAN features can be found in the MCAN User's Manual.  See section 2.4.6

Kevin Doe said:

I don’t think any overlap is possible with this config.

I agree that you should not have overlapping sections with this MRAM configuration.

Can you also share the TX message buffer contents you are trying to transmit? Perhaps there is a formatting issue there.

Can you also verify with a SPI read that all your configuration registers are getting set properly to your intended values?  For example you need to have both the INIT and CCE bits set to "1" in the Control register (0x1018) in order to set the write protected MCAN bits.  If only the INIT bit is getting set, the MCAN configuration registers won't get set when you write to them.

Are you seeing any interrupt or status bits get set during your configuration that may indicate there is an error?  Also, can you read back the MODE_SEL field to make sure you are still in Normal Mode?

Unless you have the Disable Automatic Retransmission (DAR) bit set in the Control Register (0x1018), once you set the TX buffer field in the TX Buffer Add Request (TXBAR) register, the device should try to repeatedly transmit the message until it is successfully acknowledged, or it receives too many TX errors and enters a Bus Off condition.

Regards,

Jonathan