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power supply start-up sequencing

Lorenzo Rebonato
Prodigy 20 points
Part Number: ISO1050
Other Parts Discussed in Thread: TPS62140A, , ISO1042

Hello Team,

we provide Vcc1 (+3.3V) and Vcc2 (+5V) power supplies to ISO1050 by means of two TPS62140A step-down converters, with Ratiometric and Simultaneous Start Up configuration (connected as described in SLVA470A).

The slopes of both output voltages are the same and the power supplies reach regulation in two different times, as shown in the following oscilloscope screenshot:

The soft-start time of 3.3V is about 1.1 ms. When Vcc1 reaches full regulation, Vcc2 = Vcc1 = 3.3V.

Vcc2 reaches full regulation (5V) about 1.7 ms after that EN is set.

My first question arises from the Table 8-1 at paragraph 8.3.3.3, where the device lockout and fail-safe conditions are shown:

Is this above power-up sequence sufficient in order to guarantee that the bus output remains in High Impedance (no spurious commutations of the output) and

that the Receiver output RXD is in recessive state, until Vcc2 reaches full regulation?

According to ISO1050 datasheet SLLS983K paragraph 6.3, the minimum recommended operating condition for Vcc1 is 3.0V.

During start-up, when Vcc1 reaches the minimum recommended value (3V) also Vcc2 is at 3V (1V less than the 4V threshold specified at paragraph 8.3.3.3).

Provided that Vcc1 can be considered as GOOD above 3.0V, based on Table 8-1 I understand that

- with Vcc1 >= 3V and until Vcc2 reaches 4V, the transceiver is in lockout: the bus output is kept in High Impedance and the receiver ouput RXD is in recessive state (Fail-Safe High)

- after that Vcc2 has exceeded the threshold of 4V, the device enters normal operating conditions (typically in 300µs according to the datasheet at page 21)

Please note that we provide 4K7 pull-up resistors to Vcc1 on RXD and TDX lines.

A second question is related to the voltage threshold for Vcc2, which triggers the fail-safe mode of the device: what do you meand by "about 4V"?

Is there an hysteresis provided around this threshold? If so, how much in percentage?

Also, I noted that in previous datasheet Revision J (same paragraph 8.3.3.3) the undervoltage lockout threshold for Vcc2 was 2.7V instead of 4V. Why?

This change is not mentioned in the Revision History of the document. Is this due to a functional modification of the device or die change occured after September 2019?

Looking forward to hearing from you,

Thanks and Kind Regards

Lorenzo

  • 0
    TI__Expert 8030 points

    Hi Lorenzo,

    Thanks for reaching out.

    I'm currently looking into this, and will get back to you within the next 24 hours.

    Regards,

    Kenneth

  • +1 in reply to Kenneth Arnold
    TI__Expert 8030 points

    Hi Lorenzo,

    Thank you for your patience.

    Lorenzo Rebonato said:

    Is this above power-up sequence sufficient in order to guarantee that the bus output remains in High Impedance (no spurious commutations of the output) and

    that the Receiver output RXD is in recessive state, until Vcc2 reaches full regulation?

    As stated by the datasheet, the CAN bus output pins of the device will remain in a high impedance state until around 300 µs after the VCC2 voltage crosses the 4V UVLO threshold. If 5V regulation is achieved less than 300 µs after VCC2 increases past this 4V threshold, then the device may still be in a UVLO state once full regulation is achieved. If not, then the RXD pin and the CAN Bus output pins may resume normal operation before full 5V regulation is achieved.

    Lorenzo Rebonato said:

    - with Vcc1 >= 3V and until Vcc2 reaches 4V, the transceiver is in lockout: the bus output is kept in High Impedance and the receiver ouput RXD is in recessive state (Fail-Safe High)

    - after that Vcc2 has exceeded the threshold of 4V, the device enters normal operating conditions (typically in 300µs according to the datasheet at page 21)

    Your understanding here is correct. The requirements that you have specified may be met if 5V regulation is achieved less than 300 µs after VCC2 passes the 4 V UVLO threshold.

    Lorenzo Rebonato said:

    A second question is related to the voltage threshold for Vcc2, which triggers the fail-safe mode of the device: what do you meand by "about 4V"?

    Is there an hysteresis provided around this threshold? If so, how much in percentage?

    For this device, we don't share the UVLO threshold hysteresis for this device. As mentioned by the datasheet, the ISO1050 will only enter UVLO mode if VCC2 is less than about 4 V. If you would like to use a device in which we do have hysteresis specifications for the UVLO thresholds, then we recommend that you go ahead and use our latest isolated CAN transceiver, the ISO1042. Otherwise, the only information that we can provide for the ISO1050 is that the UVLO threshold is about 4 V. 

    Lorenzo Rebonato said:

    Also, I noted that in previous datasheet Revision J (same paragraph 8.3.3.3) the undervoltage lockout threshold for Vcc2 was 2.7V instead of 4V. Why?

    This change is not mentioned in the Revision History of the document. Is this due to a functional modification of the device or die change occured after September 2019?

    This change is marked in the Revision K section of the datasheet Revision History as "Updated electrical and switching characteristics to match device performance". In this case, this line applies to multiple sections of the datasheet, and not just the specifications on page 10. 

    Regarding this change, you can now expect all ISO1050 devices have a UVLO threshold of about 4V.

    Regards,

    Kenneth