DS90UB960-Q1: some layout guide for UB960 fpdlink

Hi Yang,

The system channel specifications are in the 960 datasheet under Section 7.4.7.2 Channel Requirements. We also have a channel specification document that shows the PCB and cable loss budget as a guideline in case you are only designing one part of the system. You can allocate more budget to the cable or PCB as desired as long as the total channel requirements are met. The total channel covers all interconnecting elements from a serializer to a deserializer including all components in-between, the cable, and the PCBs. You can contact your local FAE for the full channel specs document. 

yang.chao13 said:

we place UB960 poc section near  PCB board edge，but is it  allowed for EMI and ESD performance? 

We do not recommend placing high-frequency signals near the edge of the board as it can cause EMI issues.

yang.chao13 said:

If we move 2 link poc section to TOP layer of PCB，there be  more via stub ,so dose it affect the impedance performance？

It is best to keep PoC on the same layer as the high speed RIN+ trace because vias can cause impedance discontinuities. However, if you need to route the PoC network on a different layer, make sure to keep the first PoC inductor/ferrite bead on the same layer as the high speed trace. This component should be placed orthogonally and barely touch the trace. You should also utilize GND reference vias near signal vias in order to maintain impedance through vias.

It is important to make sure that tightly-controlled 50-Ohms (+/-10%) impedance is maintained through both the high-speed channel and the PoC network to minimize reflections. You can utilize anti-pad (GND cut-out) underneath the landing pad of the PoC inductor that touches the high-speed trace to help maintain impedance.

You can refer to section 8.5 in the 960 datasheet for more layout guidelines.

Regards,

Cindy