DS90UH948-Q1: DS90UH948-Q1

Hi Jack,

Thank you for your reply.

My configuration is as follows:

- Dual link

- We are using 50MHz clock source

- The output on the deserializer is dual OLDI

- STP connection

I checked the values of the register 0x2 and after reading the bits were 0x0. For this reason I manually set the bits [7:4] to 1 and there was no change on the output, i.e. there was no image. I did check that the PDB is HIGH, output enable and sleep in register 0x2 were set to 1, LOCK pin is high.

I will try using the pattern generator to get an image on the display.

Do you perhaps see any additional checks we can do with regards to the image not being displayed on the OLED?

Regards,

Boštjan

Hi Boštjan,

Thank you for confirming your setup. Can you send the MainPage registers for the UH949 and the UH948? I want to check that the video is received properly by the UH949. 

Let me know if there is any success using the pattern generator. Are you using the 949 or the 948 pattern generator?

Best,

Jack

Hi Jack,

I am not sure which are the main page registers, so I am sending you the registers I believe you are interested in:

U948
REG | VALUE
- 0x02 | 0b11110000
- 0x24 | 0b00001000
- 0x1C | 0b00111011
- 0x28 | 0b00010001
- 0x29 | 0b00000000
- 0x49 | 0b00000001
- 0x4B | 0b00001000
- 0x64 | 0b00010000
- 0x65 | 0b00000000
- 0x37 | 0b10001001

U949
REG | VALUE
- 0x03 | 0b11010010
- 0x04 | 0b10000000
- 0x05 | 0b00000000
- 0x0C | 0b00000111
- 0x12 | 0b00000000
- 0x13 | 0b10001000
- 0x1A | 0b00000001
- 0x1E | 0b00000001
- 0x26 | 0b00000000
- 0x5A | 0b11001101
- 0x5B | 0b00100000
- 0x5F | 0b10010000
- 0x14 | 0b00000000

Please let me know if you would like me to send any additional data regarding registers.

Looking at the register values and bits, I believe that the HDMI input is valid and that the FPD link is working. I would ask you to check yourself if I am correct. I need to know where the issue is as there is the possibility that we are doing something wrong with the OLED. Any feedback will be greatly appreciated.

I tried using the pattern generator on the 948 but I could not get a pattern on the display. That is why I will focus a bit more on the display to see any possible issues. If you have any suggestions please let me know.

Thank you for all your support.

Regards,

Boštjan

Hi Boštjan,

Thank you for providing the register dumps. I have some comments

• According to the 949 register 0x5F the incoming HDMI frequency is 144MHz. What is the HDMI source you are using and are you programming the EDID on the 949?
• What is your display timing? The 948 PATGEN is limited on frequency support compared to the 949 PATGEN. I recommend using the 949 PATGEN since it can support more resolutions and frame rate

Best,

Jack

Hi Jack,

I am using the output from my laptop as the HDMI source.

I am trying to set up the timing for the OLED. I am now using the 949 to generate the pattern. I set up the M and N values for the pattern generator clock. I do this by using the PGIA and PGID registers. After I set these constants I configure the 0x65 register with 0b00000100 and the 0x64 register with 0b00110001. I am not able to get any image on the OLED for now.

Otherwise we are using our own EDID for the OLED. I write this into the 949 ram. When connected to laptop, this EDID is correctly read from the IC.

Regards,

Boštjan

Hi Boštjan,

Boštjan Brodnjak said:

I am trying to set up the timing for the OLED. I am now using the 949 to generate the pattern. I set up the M and N values for the pattern generator clock. I do this by using the PGIA and PGID registers.

Can you show me how you programming the internal timing parameters for the 949 PATGEN? Are you using the PATGEN tab on the 949 ALP or by manually programming the registers via I2C?

What's the display timing for the OLED display? If you send over the scripts you are using and the display timing is a common one, I can potentially run it on my side to make sure there is nothing missing.

Best,

Jack