SN65DSI86: DSI input error

Hi Balint,

When we see errors associated with F4 and F5 it typically has to do with AUX and HPD. However we see that the Aux passes link training. This is odd behavior. Have you tried clearing the bits and seeing if the same error bits are set.

Additionally, are you using the dsi86 calculator tool?

4786.SN65DSI86_PANEL_VIDEOREGISTER_CALC.xlsm

Balint Voros said:

- Is it correct to set up the output test mux by writing the 0xF9 register and enabling the interrupts in 0xE0 register?
- Shall I see an SOT signal when it is routed to the INT regardless other possible errors in DSI stream?

Yes to set up interrupts for the error registers you will needs to se up the 0xE_ registers to set up the masking. 

Are you able to send a schematic of your system for review?

Dear Vishesh,

Thank you for your answer and sorry for the late reply but we were on holiday due to Christmas season.

The bits set in 0xF4 and 0xF5 are not errors but status bits. In 0xF4 the 0x01 is the SEND_INT which signals the end of an AUX transmission. In 0xF5 the 0x02 is the HPD_INSERTION which means simply that the display is plugged in. I've tried to clear these status bits but it causes no change in behavior.

We were using the calculator spreadsheet for initial configuration however we tried to tweak it. Sadly I can't share the schematic but it is based on the SN65DSI86EVM schematic and on the Hardware Implementation guide.

My first question was about the setup of the output test MUX. This can be set up using the 0xF9 register which is not documented in datasheet despite its important role. The output test MUX is used to route internal signals to the interrupt pin instead of the status/error from he 0xE_ registers. I've tried to set it up with the following two commands:
- write 0x04 to 0xF9 register
- write 0x01 to 0xE0 register
As I understand a pulse should be on the INT line every time a SOT is received on DSI lanes. Is my assumption correct?

Thanks,
Balint

Hi Balint,

Could you please share the initial configuration you used and a readback of all the registers. And for the display timings and EDID, is there any difference between what the DSI video is sending compared to the test pattern used earlier?

Please give me 2-3 days to get information about your output MUX question.

Best regards,
Ikram

Hi Ikram,

I've tried to generate again with the EDID data of the display. The SN65DSI86 internal test pattern shows correctly.
I had to change only two things compared to the generated:
- I had to reverse the DP main link polarities due to routing of our PCB.
- Enabled output MUX to show SOT received on INT. (Set register 0xE0 to 0x01 and 0xF9 to 0x04)
Until this point the DSI link was not involved in the test.

After this I've entered manually the same timing data to the spreadsheet and changed the pixel clock in to 62.5MHz. Only the registers 0x12 and 0x13 (CHA_DSI_CLK_RANGE and CHB_DSI_CLK_RANGE) have been changed to 0x4B which means 375..380MHz clock range. I've updated the DSI host clock to 376MHz. Still there is no signal from DSI side, no errors in F1..F8 registers and I can't see any SOT signal on INT pin either. The SN65DSI86 internal test pattern still works. I've also attached the register readout at this stage.

In and old product with 62.5MHz pixel clock I can drive the display with 25Hz refresh rate which was enough for the display to show the right content. (This was done with a different MCU through an RGB to DP converter. No DSI was involved.)

<aardvark> 
<configure i2c=1 spi=1 gpio=0 tpower=1 pullups=0/> 
<i2c_bitrate khz=100/> 

======REFCLK Frequency  ====== 
<i2c_write addr=0x2D count=1 radix=16> 0A 4 </i2c_write>/> 

======DSI Mode  ====== 
<i2c_write addr=0x2D count=1 radix=16> 10 36 </i2c_write>/> 

======DSIA Clock  ====== 
<i2c_write addr=0x2D count=1 radix=16> 12 4B </i2c_write>/> 

======DSIB Clock  ====== 
<i2c_write addr=0x2D count=1 radix=16> 13 4B </i2c_write>/> 

======DP Datarate  ====== 
<i2c_write addr=0x2D count=1 radix=16> 94 80 </i2c_write>/> 

======Enable PLL  ====== 
<i2c_write addr=0x2D count=1 radix=16> 0D 1 </i2c_write> <sleep ms=10/> 

======Enable ASSR in Panel  ====== 
<i2c_write addr=0x2D count=1 radix=16> 64 1 </i2c_write>/> 
<i2c_write addr=0x2D count=5 radix=16> 74 0 1 0A 1 81 </i2c_write> <sleep ms=10/>

======Enable enhanced frame and ASSR in DSI86  ====== 
<i2c_write addr=0x2D count=1 radix=16> 5A 5 </i2c_write>/> 

======Number of DP lanes  ====== 
<i2c_write addr=0x2D count=1 radix=16> 93 20 </i2c_write>/> 

======Start Semi-Auto Link Training  ====== 
<i2c_write addr=0x2D count=1 radix=16> 96 0A </i2c_write> <sleep ms=20/> 

======CHA Active Line Length  ====== 
<i2c_write addr=0x2D count=2 radix=16> 20 80 07 </i2c_write>/> 

======CHB Active Line Length  ====== 
<i2c_write addr=0x2D count=2 radix=16> 22 0 0 </i2c_write>/> 

======Vertical Active Size   ====== 
<i2c_write addr=0x2D count=2 radix=16> 24 B0 04 </i2c_write>/> 

======Horizontal Pulse Width   ====== 
<i2c_write addr=0x2D count=2 radix=16> 2C 14 00 </i2c_write>/> 

======Vertical Pulse Width   ====== 
<i2c_write addr=0x2D count=2 radix=16> 30 04 00 </i2c_write>/> 

======HBP   ====== 
<i2c_write addr=0x2D count=1 radix=16> 34 40 </i2c_write>/> 

======VBP   ====== 
<i2c_write addr=0x2D count=1 radix=16> 36 10 </i2c_write>/> 

===== HFP  ====== 
<i2c_write addr=0x2D count=1 radix=16> 38 28 </i2c_write>/> 

===== VFP  ====== 
<i2c_write addr=0x2D count=1 radix=16> 3A 06 </i2c_write>/> 

===== DP-18BPP Disable  ====== 
<i2c_write addr=0x2D count=1 radix=16> 5B 0 </i2c_write>/> 

===== Color Bar Enable  ====== 
<i2c_write addr=0x2D count=1 radix=16> 3C 10 </i2c_write>/> 

===== Enhanced Frame, ASSR, and Vstream Enable  ====== 
<i2c_write addr=0x2D count=1 radix=16> 5A 0D </i2c_write>/> 

</aardvark> 

00ffffffffffff00502d4d5444150000
181d0104a51d117802de50a3544c9926
0f505400000001010101010101010101
010101010101bb3a807c70b01a402814
640026a5100000190000000000000000
00000000000000000000000000fe0049
6e666f566973696f6e0a2020000000fe
004d3133334e574644205231200a00ec

0x00: 0x36
0x01: 0x38
0x02: 0x49
0x03: 0x53
0x04: 0x44
0x05: 0x20
0x06: 0x20
0x07: 0x20
0x08: 0x02
0x09: 0x00
0x0A: 0x84
0x0B: 0x00
0x0C: 0x00
0x0D: 0x01
0x0E: 0x00
0x0F: 0x00
0x10: 0x36
0x11: 0x00
0x12: 0x4B
0x13: 0x4B
0x14: 0x00
0x15: 0x00
0x16: 0x00
0x17: 0x00
0x18: 0x00
0x19: 0x00
0x1A: 0x00
0x1B: 0x00
0x1C: 0x00
0x1D: 0x00
0x1E: 0x00
0x1F: 0x00
0x20: 0x80
0x21: 0x07
0x22: 0x00
0x23: 0x00
0x24: 0xB0
0x25: 0x04
0x26: 0x00
0x27: 0x00
0x28: 0x00
0x29: 0x00
0x2A: 0x00
0x2B: 0x00
0x2C: 0x14
0x2D: 0x00
0x2E: 0x00
0x2F: 0x00
0x30: 0x04
0x31: 0x00
0x32: 0x00
0x33: 0x00
0x34: 0x40
0x35: 0x00
0x36: 0x10
0x37: 0x00
0x38: 0x28
0x39: 0x00
0x3A: 0x06
0x3B: 0x00
0x3C: 0x00
0x3D: 0x00
0x3E: 0x00
0x3F: 0x00
0x40: 0x01
0x41: 0x00
0x42: 0x00
0x43: 0x00
0x44: 0x80
0x45: 0x00
0x46: 0xFC
0x47: 0x07
0x48: 0xCA
0x49: 0x04
0x4A: 0x54
0x4B: 0x00
0x4C: 0x14
0x4D: 0x00
0x4E: 0x14
0x4F: 0x00
0x50: 0x04
0x51: 0x00
0x52: 0x80
0x53: 0x07
0x54: 0xB0
0x55: 0x04
0x56: 0x20
0x57: 0x00
0x58: 0x40
0x59: 0xE4
0x5A: 0xFD
0x5B: 0x00
0x5C: 0x10
0x5D: 0x00
0x5E: 0x20
0x5F: 0x00
0x60: 0xA0
0x61: 0x60
0x62: 0xA4
0x63: 0x00
0x64: 0x00
0x65: 0x00
0x66: 0x00
0x67: 0x00
0x68: 0x00
0x69: 0x00
0x6A: 0x00
0x6B: 0x00
0x6C: 0x00
0x6D: 0x00
0x6E: 0x00
0x6F: 0x00
0x70: 0x00
0x71: 0x00
0x72: 0x00
0x73: 0x00
0x74: 0x00
0x75: 0x01
0x76: 0x02
0x77: 0x01
0x78: 0x80
0x79: 0x81
0x7A: 0x00
0x7B: 0x00
0x7C: 0x00
0x7D: 0x00
0x7E: 0x00
0x7F: 0x00
0x80: 0x00
0x81: 0x00
0x82: 0x00
0x83: 0x00
0x84: 0x00
0x85: 0x00
0x86: 0x00
0x87: 0x00
0x88: 0x00
0x89: 0x1F
0x8A: 0x7C
0x8B: 0xF0
0x8C: 0xC1
0x8D: 0x07
0x8E: 0x1F
0x8F: 0x7C
0x90: 0xF0
0x91: 0xC1
0x92: 0x07
0x93: 0x20
0x94: 0x80
0x95: 0x00
0x96: 0x01
0x97: 0x04
0x98: 0x01
0x99: 0x00
0x9A: 0x00
0x9B: 0x00
0x9C: 0x00
0x9D: 0x00
0x9E: 0x00
0x9F: 0x00
0xA0: 0x01
0xA1: 0xFF
0xA2: 0xFF
0xA3: 0x00
0xA4: 0x00
0xA5: 0x00
0xA6: 0x00
0xA7: 0x00
0xA8: 0x00
0xA9: 0x00
0xAA: 0x00
0xAB: 0x00
0xAC: 0x00
0xAD: 0x00
0xAE: 0x00
0xAF: 0x00
0xB0: 0x04
0xB1: 0x78
0xB2: 0xAC
0xB3: 0xAC
0xB4: 0x08
0xB5: 0x6C
0xB6: 0x9C
0xB7: 0x9C
0xB8: 0x0C
0xB9: 0x5C
0xBA: 0x5C
0xBB: 0x5C
0xBC: 0x0C
0xBD: 0x0C
0xBE: 0x0C
0xBF: 0x0C
0xC0: 0x3F
0xC1: 0x3F
0xC2: 0x0F
0xC3: 0x00
0xC4: 0x00
0xC5: 0x00
0xC6: 0x00
0xC7: 0x00
0xC8: 0x00
0xC9: 0x00
0xCA: 0x00
0xCB: 0x00
0xCC: 0x00
0xCD: 0x00
0xCE: 0x00
0xCF: 0x00
0xD0: 0x00
0xD1: 0x00
0xD2: 0x00
0xD3: 0x00
0xD4: 0x00
0xD5: 0x00
0xD6: 0x00
0xD7: 0x00
0xD8: 0x00
0xD9: 0x00
0xDA: 0x00
0xDB: 0x00
0xDC: 0x00
0xDD: 0x00
0xDE: 0x00
0xDF: 0x00
0xE0: 0x01
0xE1: 0x00
0xE2: 0x00
0xE3: 0x00
0xE4: 0x00
0xE5: 0x00
0xE6: 0x00
0xE7: 0x00
0xE8: 0x00
0xE9: 0x00
0xEA: 0x00
0xEB: 0x00
0xEC: 0x00
0xED: 0x00
0xEE: 0x00
0xEF: 0x00
0xF0: 0x00
0xF1: 0x00
0xF2: 0x00
0xF3: 0x00
0xF4: 0x00
0xF5: 0x00
0xF6: 0x00
0xF7: 0x00
0xF8: 0x01
0xF9: 0x00
0xFA: 0x00
0xFB: 0x00
0xFC: 0x00
0xFD: 0x00
0xFE: 0x00
0xFF: 0x00

Hi Balint,

Is the 62.5 MHz pixel clock rate the same as the EDID you used for the test pattern which was working? 

I am checking your initialization steps and I will get back to you shortly.

Best regards,
Ikram

Hi Ikram,

The config generated from EDID uses 150.35MHz pixel clock. After the SN65DSI86 internal test pattern was working with the 150.35MHz pixel clock I've changed it to the 62.5MHz pixel clock. The internal test pattern was still working. In the register config the only change was the CHA_DSI_CLOCK_RANGE. I try to use  CHA only.

I could not see any error or incoming signal in either case.

Thanks!

Regards,
Balint Voros

Thank you Balint, I will discuss with the team and get back to you on this.

- Ikram

Hi Balint,

To test the DSI signal, could you probe the input signals just to check that there is valid data? 

Is eDP ASSR enabled for the panel? This E2E FAQ has details for this: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/945403/faq-sn65dsi86-sn65dsi86-black-screen-debugging-guide

Also, can you please use the 0x5F register to map HSYNC and VSYNC to the GPIO pin and check whether the rates are valid? You could use a logic analyzer for this.

Best regards,
Ikram

Hi Ikram,

The ASSR is enabled and the SN65DSI86 internal test pattern shows correctly.

However I'm not sure whether the DSI signal is correct. For a test we removed the SN65DSI86 on one of the boards and we could see that there is signal on the DSI lines but we can not check the signal integrity. We have tried to check the HSYNC and VSYNC to the GPIO but we could not see any sync signal.

I've tried to route internal signals to the INT pin by setting up the 0xF9 register. I've tried to watch the a_sot_rcvd signal by setting the 0xF9 to 0x04 and enabling the IRQ by setting 0xE0 to 0x01. I could not see any SOT pulse however I'm not sure I've done this setup right and whether the SOT pulses should appear on the INT line even if the eDP setup is incorrect but the SN65DSI86 can decode the DSI input. My initial questions were based on these thoughts.

Hello,

The team is out today due to the US public Holiday.

Thank you for your patience.