DP83TD510E: Link delay and frame-to-frame jitter

André Krummenacher

Part Number: DP83TD510E

Tool/software:

Hi TI team

We are evaluating the DP83TD510E 10Base-T1L PHY to transmit encoder data to our motor controller. From the datasheet under section 5.6 Timing Requirements I found the following information:

Transmit Latency Timing: MII to CU: 750ns

Receive Latency Timing: CU to MII: 5100ns

From this I would assume the total latency from MII to MII to be 5.85us max. Is my assumption correct?

The doubt comes from the fact that the description text states "Rising edge TX_CLK with assertion TX_EN to SSD symbol on MDI" and "SSD symbol on MDI to Rising edge of RX_CLK with assertion of RX_DV".

For our application the time delay introduced by the two PHY's must be as low as possible. 5.85us is allready on the upper limit, but still workable. Low jitter is also a requirement.

Can you give us an estimation on the frame-to-frame jitter we have to expect, when using MII on both PHY's?

Thanks and best regards

André K.

17 days ago

+1 Vivaan Jaiswal 16 days ago

TI__Expert 5795 points

Hi André,

André Krummenacher said:
From this I would assume the total latency from MII to MII to be 5.85us max. Is my assumption correct?

Yes, you would be correct to assume that if using the DP83TD510 on both ends of the link, the delay due to both PHYs would not be higher than 5850ns. However, there may be other delays not due to the PHY, such as the propagation delay for the cable being used, which will need to be taken into account for the total delay between the MII interface of one PHY, to the MII interface of the Link Partner PHY.

Unfortunately, we do not have any jitter values for this device, only the maximum latency values listed in the datasheet.

Best,

Vivaan

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DP83TD510E: Link delay and frame-to-frame jitter