DS92LV2422: Double Data Rate - data update on both clock edges

Hello,

I need serializer/deserializer combination for at least 20 (or more) bit wide parallel bus with data update on both clock edges (seen at the output – input doesn’t matter).

Maxim's MAX9273 has a feature called DBL (double) for example (but too few bits).

Is it possible to use DS92LV2422 and a d-type flip-flop (say SN74LVC1G74) for emulation of double data rate.

Are there any suggestion or new parts?

Sure I will not win data rate doing this - we need about 25..28MHz double data rate clock and 50..56MHz at single clock.

Thank you & greetings michael