DS90LV804: Buffering a FPGA to FPGA data connection

I am looking for a solution to buffer a 5-channel (4 data channels + 1 clk) LVDS link between 2 FPGAs.

The LVDS clock is around 74 MHz; data rate is around 300 Mbps.

Is it possible to use DS90LV804 for the data lines and DS90LV001 for clk or will the different  ICs create too much skew?