ISO1042-Q1: glitch on startup

Hi Ross,

Thanks for reaching out.

Is it possible to share a waveform plot (VCC1, TXD, CANH, CANL) indicating voltage and time scales for all signals? In the shared waveform, I could see two Y-axes on the left, one in green and the other in blue. Assuming green Y-axis is for green power plot, the voltage seems to be around 14V. This could be the battery voltage, it would be best if you could monitor VCC1/VCC2 to better compare the results for debugging.

I also see that the amplitude of the pulse in magenta waveform to be around 2V. Assuming magenta waveform to be TXD, I believe the cause for such lower voltage on TXD is probably the VCC1 voltage being not settled to 3.3V yet. Hence, need VCC1 waveform along with TXD and CANH/CANL to better understand the behavior for debug purposes.

Ross Parlour said:

This is happening on power up of the inverter (around 30ms from power ON) and before the MCU starts initializing the IO’s.

The device only requires about 100µs for power up, 30ms is much beyond the expected power-up time. Hence, this glitch can't be referred as power-up glitch and needs to be investigated to understand what in the system is causing this pulse.

I didn't see any concerns in the schematic. I am assuming that customer has followed ISO1042 datasheet guidelines to place the decaps close to device supply pins, preferably within 2mm distance.

Please do share the requested information to help debug the issue, thanks.

Regards,
Koteshwar Rao

Hi Ross,

To help debug the issue and find a resolution, please do help us with the information requested in my previous post. Thanks.

Regards,
Koteshwar Rao

Hi Koteshwar,

Please see the requested data below. Note that VCC1 = +3V3_ISO (dark blue trace) and VCC2 = +5V (brown trace).

The magenta trace in the previous data is CAN_H – CAN_L (differential measurement).

They have also discovered that if they reverse the power supply sequence (power VCC1 before VCC2) then the glitch at start up does not occur. That said, changing the power supply sequence is not an easy fix without making significant hardware changes so if there’s another way around this then they will be very interested.

Please let me know if you need any more info?

Ross

Hi Ross,

Thanks for sharing waveform of VCC1, VCC2, TXD and CAN signals and clarifying about the magenta plot from the previous waveform.

My intention of asking these plots is to know when do the CAN signals go dominant in relation to their respective VCC ramps. Hence, I would need to see VCC1, VCC2, TXD and maybe one CAN line to figure out if this glitch is happening during the ramp. You did share that the glitch was happening abbut 30ms after the ramp of 14V but it isn't clear if it is still 30ms after VCC1/VCC2 or if it happening during the ramp.

Ross Parlour said:

In this waveform capture, I see TXD is held HIGH (5V) all the time even when VCC1 is ramping from 0V to 3.3V. Could you please confirm if this is how the device is being operated? If yes, then this is violated TXD pin abs max rating and hence, the device behavior could be different from what is expected.

The max voltage at TXD should never VCC1+0.5V. This means, when VCC1 = 0V, TXD shouldn't be more than 0.5V. If TXD exceeds this then it could possibly either partially or fully power-up VCC1 through the ESD bypass diode and could lead to unexpected behavior.

Even otherwise, it looks VCC1 is 3.3V while TXD is 5V. This also violates abs max rating of TXD and could lead to incorrect behavior of device and also damage the ESD diode along any associated nearby circuit.

Please do help confirm if my understanding above is correct and also do share the waveform requested. Thanks.

Regards,
Koteshwar Rao