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SN74HCS594: Hold time requirement of RCLK w.r.t. nSRCLR

Sven Probst
Expert 1630 points
Part Number: SN74HCS594
Other Parts Discussed in Thread: SN74LVC1G04

Dear TI experts,

we want to use a chain of SN74HCS594 devices as an IO expander controlled via SPI. The clock of the parallel output register (of all devices in the chain) will be connected to the !CS signal. It would be convenient for us to clear the shift register by !SRCLR while !CS is high (e.g. by using an inverter), to have a defined shift register content when communication is restarted.

Is there a timing requirement after the rising edge of RCLK until the shift register is cleared by !SRCLR, so that the (un-cleared) shift register contents are stored in the output register?

I am aware of the "!SRCLR low before RCLK↑" setup time specification, but I think that is the time required to copy the cleared shift register contents to the output register, so all outputs low. Correct?

  • 0
    Guru 243980 points

    Similar considerations exist for "SRCLK↑ before RCLK↑". There is no specification that says how large the time can be for guaranteeing that the new shift register value is not copied to the output register, but the datasheet says:

    If both clocks are connected together, the shift register is one count pulse ahead of the storage register.

    So I'd say that if the falling edge of SRCLR happens shortly after the rising edge of RCLK (because of the propagation delay of the inverter), you're safe. If you want to be really sure, use more inverters.

  • 0 in reply to Clemens Ladisch
    Expert 1630 points

    Thank you very much for your guess. I agree with you. But I don't want to develop a product based on assumptions - that could get pretty expensive if the assumptions are wrong.

    Maybe TI can clarify that?

  • +1 in reply to Sven Probst
    TI__Guru* 96591 points

    Hi Sven,

    I agree with you both that there _probably_ isn't anything to worry about here. To be clear - my understanding is that your concern is that SRCLR\ will clear the shift register data before RCLK has the chance to load that data into the output registers - or it may corrupt _some_ of the data.

    Sven Probst said:
    Is there a timing requirement after the rising edge of RCLK until the shift register is cleared by !SRCLR, so that the (un-cleared) shift register contents are stored in the output register?

    I don't have a timing specification that covers exactly what you're asking. 

    We can look at the timing of the device to find a way to do this within the datasheet spec though. Using 2V values (because they exaggerate the differences), the propagation delay for SRCLR\ to the output is 55ns (max) and for RCLK it's 45ns. The two paths are pretty similar:

    Basically only going through one level of DFF each.  As long as the RCLK pulse happens first, the outputs will receive the correct data - but I can understand your concern as this is a pretty close race, and in a production design I would also want to avoid that issue entirely.

    The plus side is that this device already has Schmitt-trigger inputs, so adding some delay is as easy as adding an RC to the input.  If you can add about 50ns of delay -- assuming it doesn't impact your timing requirements -- this would ensure that there's no chance of issues under any circumstances.

    Using a typical capacitor value of 22pF, I'd go with a 1.5k resistor to get around 50ns of delay. This combined with the internal delay of the inverter should guarantee that you won't see any problems under any corner conditions.

    You _could_ use only a resistor (10k) and count on the input capacitance of the device to provide the other part of the RC, but I would go with an external capacitor to make that more predictable and stable.

    I drew up both options in a simulation:

  • 0 in reply to Emrys Maier
    Expert 1630 points

    Hello Emrys,

    yes, your understanding of my request is correct.

    Since our use case does not seem to be too rare and the logic family is new, TI might consider adding this specification. Could you submit this request?

    In the meantime, I will check our timing requirements related to !CS becoming active (low) and the first rising edge of SRCL (start of transmission). If it fits, I will add the RC you suggested.

  • 0 in reply to Sven Probst
    TI__Guru* 96591 points

    Hi Sven,

    I'll discuss with my systems engineer for future projects, however adding a specification like this isn't just a quick change -- it requires a full re-characterization across process variations. Due to cost and resource availability, it's unlikely that this device will get a spec like that any time soon.

    I'm looking into doing some simulations to give you greater confidence on doing this directly (without the RC), however I won't be able to provide any guarantees going that way. I might write up an app note on my findings to provide documentation that can be referred to, depending on how definitive the results seem to be.

  • 0 in reply to Emrys Maier
    Expert 1630 points

    Hi Emrys,

    thank you for your support. I am looking forward to your findings.

  • 0 in reply to Sven Probst
    TI__Guru* 96591 points

    Hi Sven,

    I was able to run some simulations and I'm seeing that the device can very reliably store the data into the output registers so long as the clear signal activates after RCLK. With the added delay of the inverter, I don't think there should be any concern with this application.

    Can you give me details of your application so that I can run more targeted simulations? I need your Vcc value, Vcc tolerance, and operating temperature range

    Just so you know - one set of sims for this will take about a day to setup and run, however I would consider the results very reliable.

  • 0 in reply to Emrys Maier
    Expert 1630 points

    Hi Emrys,

    thank you very much for running the simulations. Our Vcc is 3.15V .. 3.3V. The PCB temperature will be 20°C .. 55°C. The temperature of inverter and SN74HCS594 will be almost the same. I'm considering to use the SN74LVC1G04 due to its 3.3V specification. But HCS family is also an option. Our chain consists of 3 SN74HCS594 connected to the same inverter output.

    You don't have to hurry with the simulation - design of the PCB will be finished in about a month.

    Once more, thank you for your great efforts.

  • 0 in reply to Sven Probst
    TI__Guru* 96591 points

    I went ahead and ran the simulation from 3V to 3.6V to capture your voltage range plus a little extra wiggle room, and also from -40 to +125C.

    This was a simplified version of the model which is much faster, but still shouldn't vary much from the final results -- but I thought I'd just give you an update.

    Even when SRCLR\ goes low at exactly the same time as RCLK goes high, I still see that the serial register data is properly stored into the output registers before the serial registers are cleared. With any added external delay, I would have zero concerns with using an inverter between these two pins for control.

    It will take a day or so to complete all my simulations on the 'best' version of the model, but I expect that we will see the same results. I'll plan to post waveforms for you on Monday, assuming nothing goes wrong with my sims over the weekend.

  • +1 in reply to Emrys Maier
    TI__Guru* 96591 points

    This is the result with the following parameters:

    RCLK rising edge at the same time (0 delay) as the SRCLR\ falling edge.

    VCC = 3V, 3.6V

    -40 to +150C (junction temperature)

    Process corners for weak and strong material

    The device is consistently able to read the data before it is cleared under these conditions.