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SN74LVC1G11: AND gate: Functional Safety FIT Rate, Failure Mode Distribution for safety system

Michael van der Bend
Prodigy 20 points
Part Number: SN74LVC1G11
Other Parts Discussed in Thread: SN74LVC1G08

I am looking for a design where I can connect 2 safety signals to 1 safety input on a MCU. 

Voltage levels are 3V3. When either one of the safety signals drops to 0V/floating, the MCU input should do the same.

A logical step would be to use an AND gate, for example, the SN74LVC1G11. Being a safety system, we need to analyze the weaknesses in the system. 

In order to implement this AND gate, we need to be sure that all failure modes of the Gate are considered safe. In other words, the output cannot be stuck at VCC when either input is low.

This particular AND gate shows great MTBF values, but I do not see a Failure Mode Distrubution (FMD) report. I did find one for the SN74LVC1G08, which does not look very promising for my application. 

https://www.ti.com/lit/fs/scea075/scea075.pdf?ts=1675416693627&ref_url=https%253A%252F%252Fwww.google.com%252F

I am wondering if it is possible to find an AND gate without failure modes that could short the output to VCC.

  • +1
    TI__Guru* 96862 points

    Hi Michael,

    Michael van der Bend said:
    This particular AND gate shows great MTBF values, but I do not see a Failure Mode Distrubution (FMD) report. I did find one for the SN74LVC1G08, which does not look very promising for my application. 

    If we were to make one for the LVC1G11, you would find it identical to the LVC1G08 report you have already seen. These devices, along with all other CMOS logic gates, are extremely similar.

    Michael van der Bend said:
    I am wondering if it is possible to find an AND gate without failure modes that could short the output to VCC.

    No, not that I know of. Failure of logic is extremely rare, as you pointed out, and almost every time I've seen a failure it was caused by our customer's design and not an issue with the quality, manufacturing, or design of our device. All of our modern logic is built the same way using monolithic silicon, CMOS, and no redundancy, isolation, or specific failure modes 'built in.'  I also do not know of any logic gates that include those features.

    The most common mode of failure I have seen is a short to ground through the ESD protection structure due to electrical overstress - ie being damaged by the system from either excessive current or a huge ESD event.

    The best thing you can do for safety with logic is to keep your input / output voltages and currents within the datasheet specifications and protect ports with system-level ESD.

    If you want devices that have a more controlled construction and more tests on our side, you can go up in grade from Q1 to EP or MIL. Neither of those ratings will guarantee failure modes though - they will just reduce the likelihood of an early failure due to quality.