SN74VMEH22501A: Design guidelines for live insertion using Power-Up 3-State (PU3S) Circuits

GAURAV UPADHYAY

Prodigy 70 points

Part Number: SN74VMEH22501A

Tool/software:

Hi Everyone,

I need some clarification for below image: (*Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices)

Query: If i make change the logic of OE as per PU3S then i will impact my transparent mode condition or not?

Second Query, how can i achieve below highlighted power sequence in my design? Please share any documents for this.

Please share your comments.

Thanks,

Gaurav

1 month ago

+1 Clemens Ladisch 1 month ago

Guru 267310 points

1. As long as /OE is high, the output is disabled.

2. You need to connect /OE to VCC with a pull-up resistor, and pull it down later (usually with a GPIO of the MCU) when the circuit has powered up.

0 GAURAV UPADHYAY 1 month ago in reply to Clemens Ladisch

Prodigy 70 points

Hi Clemens,

Thanks for your response.

GAURAV UPADHYAY said:
Second Query, how can i achieve below highlighted power sequence in my design? Please share any documents for this.

Please provide your input on second query also. How to achieve highlighted power sequence in hardware design?

Thanks,

Gaurav

+1 Malcolm Lyn 1 month ago in reply to GAURAV UPADHYAY

TI__Genius 17260 points

Hi Gaurav,

Typically you would do this with a power sequencing subsystem. Designing that subsystem is a little beyond the scope of this forum but typically involves a microcontroller or FPGA to enable some set of load switches.

Best,

Malcolm

0 GAURAV UPADHYAY 1 month ago in reply to Malcolm Lyn

Prodigy 70 points

Thanks a lot Malcolm for response.

Thanks,

Gaurav

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SN74VMEH22501A: Design guidelines for live insertion using Power-Up 3-State (PU3S) Circuits