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[FAQ] What is the default output of a latched device? (Flip-Flop, latch, register)

FAQ: Logic and Voltage Translation > Output Parameters >> Current FAQ

Flip-flops, latches, and registers do not have a default state on power up.  The output is in an 'unknown' state until data is clocked through.

This is because the underlying latch circuit used to store the output value is inherently unstable at startup.  It could become a HIGH or a LOW at the output, and the value is impossible to determine before it is measured.

The most basic CMOS latch circuit is shown here:

When Vcc = 0V, all values in the CMOS circuit are 0V and it's easy to determine the output (0V), however as the supply increases, it becomes impossible to know which side of the latch will be "HIGH" and which side will be "LOW" when the system reaches steady state without additional information. It's very easy for a latch like this to have different states on each successive startup.

Due to imperfections in manufacturing and system loading, it is possible for a latch to appear to start the same way every time, even when tested many times. It is important to note that this does _not_ guarantee that the output will _always_ be that value. Different devices can have different imperfections that can result in a different "default" output state, and this state can be changed by system loading. Lingering charge in a system very commonly will determine the state of a latch at startup.