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LP-AM243: MCAN module bit timings configuration and functional clock

Antonio Di Maggio
Prodigy 30 points
Part Number: LP-AM243
Other Parts Discussed in Thread: SYSCONFIG

Dear TI Experts,

I am dealing with bit timing configuration for MCAN module on the LPAM243 demo board.

After reading the Technical Reference Manual my understanding is that the CAN bit-time depends on the functional clock period, and after some debug i was able to discover that the functional clock frequency is set to 80MHz in the auto-generated file ti_power_clock_config.c from the sysconfig.
But i am not able to find any configuration from the Sysconfig GUI regarding this value and since we are developing aur custom-board i want to gain a deeper understanding of how it works.

Well, here are my questions:

  • How is possible to configure the MCAN functional clock frequency since Sysconfig does not seem to be useful?
  • Why the MCAN_initSetBitTimeParams function set to default values the MCAN_DBTP and MCAN_NBTP registers regardless of the functional clock frequency? Shall the functional clock frequency be always the same value (80MHz)?

Best regards

  • 0
    TI__Mastermind 29198 points

    Hi,

    I'm looking into this and will get back with you shortly.

    Regards,
    Frank

  • 0 in reply to Frank Livingston
    TI__Mastermind 29198 points

    Hi Antonio,

    There is an MCAN FCLK source select mux configured by these registers:

    CTRLMMR_MCAN0_CLKSEL[1-0] CLK_SEL
    CTRLMMR_MCAN1_CLKSEL[1-0] CLK_SEL

    Please see the AM64x/AM243x TRM (spruim2c.pdf):

    • Figure 12-2076. MCAN[0-1] Integration
    • Table 5-9. Summary of the Clock Muxing and Division Registers
    • Table 5-692. CTRLMMR_MCAN0_CLKSEL Instances
    • Table 5-694. CTRLMMR_MCAN1_CLKSEL Instances

    For MCAN0/1, the default CLK_SEL value is 0, which selects MAIN_PLL0_HSDIV2_CLKOUT (note: this is incorrectly shown as MAIN_PLL0_HSDIV3_CLKOUT in Table 5-693 & 5-695). MAIN_PLL0_HSDIV2_CLKOUT can be configured (via PLL0 HSDIV2) for 80, 40, or 20 MHz output, where the default is 80 MHz.

    Changing the clock source (the mux value) or the clock frequency for a particular selected clock (e.g. 80,40,or 20 MHz for MAIN_PLL0_HSDIV2_CLKOUT) requires the R5F to request the change from SYSFW via Sciclient calls. I notice the SDK SOC module API has functions for setting the clock frequency for a particular module (MCAN in this case) using Sciclient. Please see:

    I haven't used the SOC API functions yet (I've always used Sciclient calls directly in my code). I'll experiment with these functions in one of the MCAN loopback examples. In the meantime, can you try them on your own?

    I don't see a way to configure MCAN FCLK from Sysconfig, but I agree with you that Sysconfig should have this feature. I'll take this up with the software development team.

    Regards,
    Frank

  • +1 in reply to Frank Livingston
    TI__Mastermind 29198 points

    Hi Antonio,

    Source code for SOC_moduleSetClockFrequency() is located in these files:

    • source/drivers/soc/am64x_am243x/soc.h:87:int32_t SOC_moduleSetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t clkRate);
    • source/drivers/soc/am64x_am243x/soc.c:90:int32_t SOC_moduleSetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t clkRate)

    Module & Clock ID's are located here:

    The SOC_moduleSetClockFrequency() function changes the "parent" clock for the selected clock until it finds a "parent" clock which can be set to the requested frequency, or finds no such "parent" clock. The "parent" clocks are the inputs to the clock mux in Figure 12-2076. MCAN[0-1] Integration.

    To change the MCAN FCLK to 40 MHz, I added the following function call to the main() in mcan_loopback_interrupt_am243x-lp_r5fss0-0_nortos_ti-arm-clang() before the call to mcan_loopback_interrupt_main():

    // FL: change MCAN FCLK to 40 MHz
status = SOC_moduleSetClockFrequency(
            TISCI_DEV_MCAN0 ,
            TISCI_DEV_MCAN0_MCANSS_CCLK_CLK,
            40000000);

    I checked the following before and after the call to SOC_moduleSetClockFrequency()

    • CTRLMMR_MCAN0_CLKSEL at address 0x43008480 : inspected via CCS memory window
    • MAIN_PLL0_HSDIV2_CLKOUT : checked via GEL script "Get_All_PLL_Configurations"

    Before

    • CTRLMMR_MCAN0_CLKSEL = 0x00000000 => MAIN_PLL0_HSDIV2_CLKOUT selected from mux
    • PLL0,HSDIV #2's divider value is: 25 => MAIN_PLL0_HSDIV2_CLKOUT = 80 MHz

    After

    • CTRLMMR_MCAN0_CLKSEL = 0x00000000 => MAIN_PLL0_HSDIV2_CLKOUT selected from mux
    • PLL0,HSDIV #2's divider value is: 50 => MAIN_PLL0_HSDIV2_CLKOUT = 40 MHz

    Please see the TRM, 5.4.5.2 MAIN Domain PLLs Overview for details on how the clock frequencies are generated. In this case, MAIN_PLL0_HSDIV2_CLKOUT is calculated as follows:

    FOUTP = (FREF / REF_DIV) * (FB_DIV + FB_DIV_FRAC)
    MAIN_PLL0_HSDIV2_CLKOUT = FOUTP / PLL0_HSDIV2

    MCAN FCLK 80 MHz:

    FOUTP = (25e6 / 1) * (80 + 0) = 2e9
    MAIN_PLL0_HSDIV2_CLKOUT = 2e9 / 25 = 80e6, 80 MHz

    MCAN FCLK 40 MHz:

    FOUTP = (25e6 / 1) * (80 + 0) = 2e9
    MAIN_PLL0_HSDIV2_CLKOUT = 2e9 / 50 = 40e6, 40 MHz

    Regards,
    Frank

  • +1
    TI__Mastermind 29198 points
    Antonio Di Maggio said:
    Why the MCAN_initSetBitTimeParams function set to default values the MCAN_DBTP and MCAN_NBTP registers regardless of the functional clock frequency? Shall the functional clock frequency be always the same value (80MHz)?

    This function only sets default values assuming a 80 MHz MCAN FCLK and Nominal/Data bit-rates of 1 Mbps/500 kbps. The function MCAN_setBitTime() writes the values in the MCAN_BitTimingParams structure to the MCAN_DBTP & MCAN_NBTP registers. The values in the structure can be overwritten before the call to MCAN_setBitTime().

    Regards,
    Frank