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TMS570LS3137: Questions about SRAM2 BIT ECC fault injection for TMS570LS3137?

zhang xiaohong
Intellectual 730 points
Part Number: TMS570LS3137

hi，When testing SRAM 2bit ECC fault injection, under normal circumstances, the interruption of ESM3.3 and ESM3.5 should be triggered. However, according to the debugging and printing information, the FLASH of ESM3.7 also caused an uncorrectable error, but I did not cause the FLASH fault. What is the reason for this? Is it normal? thanks a lot.

  • 0
    TI__Guru**** 186196 points
    zhang xiaohong said:
    but I did not cause the FLASH fault. What is the reason for this? Is it normal?

    Do you mean that the bit 8 of FEDACSTATUS is not set? This bit should be set if there is 2-bit ECC error.

  • 0 in reply to QJ Wang
    Intellectual 730 points

    I still don't understand, why when testing SRAM_ECC_ERROR_FORCING_2BIT or SRAM_ECC_2BIT_FAULT_INJECT, an uncorrectable FLASH error occurs? Isn't the 2BIT fault of SRAM and the 2BIT fault of FLASH not detected independently by SECDED?

  • 0 in reply to QJ Wang
    Intellectual 730 points

    Another problem is that when the SRAM_ECC_ERROR_FORCING_2BIT test is performed, the test result fails, and the debugging information is printed. When it is found that bit3 of SR1[2] is not set, but the data abort interrupt is entered, but this flag is It is not set。

    SR1[2] should be 0x28 normally, but the print result is 0x20, and the return result of the test function is also a failure.I don't understand what is the effect between the two.

    Please reply，Thanks a lot.

    Later, I blocked the abnormal response condition statement to FLASH, and I found that the test can pass. What is the reason? Is the test failed due to the abnormal FLASH interrupt generated during the SRAM 2BIT test?

  • 0 in reply to zhang xiaohong
    TI__Guru**** 186196 points

    Hi Xiaohong,

    zhang xiaohong said:
    why when testing SRAM_ECC_ERROR_FORCING_2BIT or SRAM_ECC_2BIT_FAULT_INJECT, an uncorrectable FLASH error occurs?

    The bit of FEDACSTATUS should not be set for SRAM ECC error, but it is set for Flash ECC error. 

    My message in my last post is to say that the "This bit should be set if there is 2-bit FLASH ECC error."

  • 0 in reply to QJ Wang
    TI__Guru**** 186196 points
    zhang xiaohong said:
    What is the reason? Is the test failed due to the abnormal FLASH interrupt generated during the SRAM 2BIT test?

    Since the ESM3.7 is set, the "else if((ESM_GRP3_MASK == ((grp_channel&ESM_GRP3_MASK)))&&(ESM_G3ERR_FMC_UNCORR == (grp_channel & 0x0000ffff)))" becomes true. Can you check when the ESM3.7 is set, before SRAM selftest or during SRAM selftest? 

    The bit 3 and bit 5 of SR[2] are caused by 2-bit ECC error on Even address and Odd address.

    Even address is: 0x08000000 + N*0x08      where N=0,2,4,6,8,...

    Odd address is: 0x08000000 + N*0x08       where N=1,3,5,7,...