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LAUNCHXL2-RM46: DCAN configuration and test mode

Daniel Arce
Prodigy 10 points
Part Number: LAUNCHXL2-RM46

Hello, we are working on DCAN implementation in the LAUNCHXL2-RM46. We tested the Loopback mode and the LoopBack Combined with Silent Mode properly (Attached I send the signal seen from the Tx Port). However, the implementation of silent mode test and not test mode by the connection between Tx and Rx are not working. It seems that the Rx pin is not connected to the peripheral because when using it, we have not seen any type of information in the RAM either signal on the signal analyzer. We tested these configurations with DCAN1 and DCAN2 (canInit function attached here) and we obtained the same response.

. 

void canInit(void)
{
/* USER CODE BEGIN (4) */
/* USER CODE END */
    /** @b Initialize @b CAN1: */

    /** - Setup control register
    *     - Disable automatic wakeup on bus activity
    *     - Local power down mode disabled
    *     - Disable DMA request lines
    *     - Enable global Interrupt Line 0 and 1
    *     - Disable debug mode
    *     - Release from software reset
    *     - Enable/Disable parity or ECC
    *     - Enable/Disable auto bus on timer
    *     - Setup message completion before entering debug state
    *     - Setup normal operation mode
    *     - Request write access to the configuration registers
    *     - Setup automatic retransmission of messages
    *     - Disable error interrupts
    *     - Disable status interrupts
    *     - Enter initialization mode
    */
    canREG1->CTL = (uint32)0x00000200U 
                 | (uint32)0x00000000U 
                 | (uint32)((uint32)0x00000005U  << 10U)
                 | (uint32)0x00020043U;

    /** - Clear all pending error flags and reset current status */
    canREG1->ES |= 0xFFFFFFFFU;

    /** - Assign interrupt level for messages */
    canREG1->INTMUXx[0U] = (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U;

    canREG1->INTMUXx[1U] = (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U
                         | (uint32)0x00000000U;

    /** - Setup auto bus on timer period */
    canREG1->ABOTR = (uint32)4U;

    /** - Initialize message 1 
    *     - Wait until IF1 is ready for use 
    *     - Set message mask
    *     - Set message control word
    *     - Set message arbitration
    *     - Set IF1 control byte
    *     - Set IF1 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF1STAT & 0x80U) ==0x80U)
    { 
    } /* Wait */


    canREG1->IF1MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x1FFFFFFFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF1ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x00000801U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)6U;
    canREG1->IF1CMD  = (uint8) 0xF8U;
    canREG1->IF1NO   = 1U;

    /** - Initialize message 2 
    *     - Wait until IF2 is ready for use 
    *     - Set message mask
    *     - Set message control word
    *     - Set message arbitration
    *     - Set IF2 control byte
    *     - Set IF2 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF2STAT & 0x80U) ==0x80U)
    { 
    } /* Wait */

    canREG1->IF2MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x1FFFFFFFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF2ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x00000801U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)6U;
    canREG1->IF2CMD  = (uint8) 0xF8U;
    canREG1->IF2NO   = 2U;

    /** - Setup IF1 for data transmission 
    *     - Wait until IF1 is ready for use 
    *     - Set IF1 control byte
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF1STAT & 0x80U) ==0x80U)
    { 
    } /* Wait */
    canREG1->IF1CMD  = 0x87U;

    /** - Setup IF2 for reading data
    *     - Wait until IF1 is ready for use 
    *     - Set IF1 control byte
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF2STAT & 0x80U) ==0x80U)
    { 
    } /* Wait */
    canREG1->IF2CMD = 0x17U;

    /** - Setup bit timing 
    *     - Setup baud rate prescaler extension
    *     - Setup TSeg2
    *     - Setup TSeg1
    *     - Setup sample jump width
    *     - Setup baud rate prescaler
    */
    canREG1->BTR = (uint32)((uint32)0U << 16U) |
                   (uint32)((uint32)(6U - 1U) << 12U) |
                   (uint32)((uint32)((3U + 6U) - 1U) << 8U) |
                   (uint32)((uint32)(4U - 1U) << 6U) |
                   (uint32)19U;


     /** - CAN1 Port output values */
    canREG1->TIOC =  (uint32)((uint32)1U  << 18U )
                   | (uint32)((uint32)0U  << 17U )
                   | (uint32)((uint32)0U  << 16U )                
                   | (uint32)((uint32)1U  << 3U )  
                   | (uint32)((uint32)1U  << 2U )    
                   | (uint32)((uint32)1U << 1U );
                   
    canREG1->RIOC =  (uint32)((uint32)1U  << 18U )    
                   | (uint32)((uint32)0U  << 17U )  
                   | (uint32)((uint32)0U  << 16U )   
                   | (uint32)((uint32)1U  << 3U )  
                   | (uint32)((uint32)0U  << 2U )
                   | (uint32)((uint32)0U <<1U );        

    /** - Leave configuration and initialization mode  */
    canREG1->CTL &= ~(uint32)(0x00000041U);
}

Thanks for your support.

Daniel

  • 0
    TI__Guru**** 186196 points
    Daniel Arce said:
    However, the implementation of silent mode test and not test mode by the connection between Tx and Rx are not working.

    Silent mode is one of the test modes. For all test modes, the Test bit in the CAN Control Register needs to be set to 1. This enables write access to the Test Register.

    Silent Mode is activated by setting the Silent bit in Test Register to 1. 

    So using Silent Mode requires that both the Test bit and the Silent bit are set.

  • 0 in reply to QJ Wang
    Prodigy 10 points

    Hello QJ, thanks for your response.
    Yeah, we are using a function that changes the TEST bit in the CTL register and setup the Silent mode pin in the TEST register. However, this specific configuration (silent mode) is not working. Information is not in the RAM or even in the physical pin. Other test configurations are working properly. The problem is related to the connection between the peripheral and the physical pin.

    Daniel

  • 0 in reply to Daniel Arce
    TI__Guru**** 186196 points

    Hi Daniel,

    I didn't test silent mode before, but I will try next week and let you know my test result.

  • 0 in reply to QJ Wang
    TI__Guru**** 186196 points

    Just did a quick test. It works as expected: rxed data = txed data

  • 0 in reply to QJ Wang
    Prodigy 10 points

    Hello QJ, thank you for your response.

    We have done test with L_back without problems. However, we want to know if as datasheet mentioned, it is possible activate silent mode without L_back, because we dont have response in Rx.

  • +1 in reply to Daniel Arce
    TI__Guru**** 186196 points

    Hi Daniel,

    The Silent mode is that the TX pin is internally wire-and with the RX pin while driving only recessive bits on the TX pin. The DCAN is still able to receive valid data frames and valid remote frames, but it will not send any dominant bits. 

    You are right. If loopback mode (LBK+Silent) is not enabled, you won't get RX interrupt and data because it doesn't transmit any valid data.

  • 0 in reply to QJ Wang
    Prodigy 10 points

    Ok, perfect

    Thank you QJ. I think that now we can continue with our project considering this information.

    Best regards

    Daniel