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TM4C129XNCZAD: Identifying failure of the main oscillator (MOSC)

Jason Reeder
Genius 10435 points
Part Number: TM4C129XNCZAD

My customer has the following questions:

I am currently working with the TM4C129XNCZAD microcontroller, using an external oscillator at 25 Mhz.

My doubt is around the identification of the failure of the main oscillator (MOSC) when it is not working in the appropriate range of frequencies.

 

I discover there is the possibility to configure the main oscillator verification circuit setting the CVAL bit in the register

MOSCCTL. My questions are:

  • Does the verification circuit works just during the startup phase or also while the microcontroller is running?

For example if i detach the external crystal from the circuit after it powers up and runs correctly, does the MOSC verification raise a failure event?

  • The verification circuit checks whether the oscillator is working in the allowed range from 5 to 25 Mhz or whether the attached crystals is working in its correct range around 25 Mhz? And if yes, how can we choose the range to check?
  • If i do NOT set the CVAL bit in the MOSCCTL, is there another monitor for the main oscillator failure?
  • The MOSCIM bit of MOSCCTL has effect only if the CVAL is previously set?
  • 0
    TI__Guru*** 132565 points

    Hello Jason,

    Jason Reeder said:
    Does the verification circuit works just during the startup phase or also while the microcontroller is running?

    The main oscillation monitoring occurs while the MCU is running as well. Disconnecting or disrupting the oscillator input to the MCU should trigger the failure event.

    Excerpt from the Datasheet: The clock control includes circuitry to ensure that the main oscillator is running at the appropriate frequency. The circuit monitors the main oscillator frequency and signals if the frequency is outside of the allowable band of attached crystals.

    Jason Reeder said:
    The verification circuit checks whether the oscillator is working in the allowed range from 5 to 25 Mhz or whether the attached crystals is working in its correct range around 25 Mhz? And if yes, how can we choose the range to check?

    It will monitor for variation based on the selected crystal that was provided as part of the clock configuration, not across the entire range of allowed clock frequencies. Therefore it is important to select the correct supported crystal frequency as part of configuration or else it will always fail to start the oscillator.

    Jason Reeder said:
    If i do NOT set the CVAL bit in the MOSCCTL, is there another monitor for the main oscillator failure?

    There is not.

    Jason Reeder said:
    The MOSCIM bit of MOSCCTL has effect only if the CVAL is previously set?

    Correct.

    With those answers given...

    I always get a little suspicious when I heard MOSC and 'Failure' associated together. I would recommend checking if the customer is trying to use the MOSC as the OSCCLK source for the system.

    If they are, then likely what triggered these questions is that they are hitting Errata SysCtl#23 which can cause a bus fault on reset: https://www.ti.com/lit/er/spmz850g/spmz850g.pdf#page=84

    Best Regards,

    Ralph Jacobi

  • 0 in reply to Ralph Jacobi
    TI__Genius 10435 points
    Ralph Jacobi said:
    Jason Reeder said:
    The verification circuit checks whether the oscillator is working in the allowed range from 5 to 25 Mhz or whether the attached crystals is working in its correct range around 25 Mhz? And if yes, how can we choose the range to check?

    It will monitor for variation based on the selected crystal that was provided as part of the clock configuration, not across the entire range of allowed clock frequencies. Therefore it is important to select the correct supported crystal frequency as part of configuration or else it will always fail to start the oscillator.

    How the MOSCFAIL into RESC register turns into ‘1’ condition? Our scope is to monitor the oscillator, i.e. if the 25Mhz we’re using derives in 24Mhz, is there any failure alarm/flag that inform the uC about that variation? I’m referring about a condition in which CVAL is active (‘1’) and we’re monitoring the RESC register.

  • 0 in reply to Jason Reeder
    TI__Guru*** 132565 points

    Hello Jason,

    So digging into this further, I learned more about the process here.

    Regarding prior comments I made:

    Ralph Jacobi said:
    It will monitor for variation based on the selected crystal that was provided as part of the clock configuration, not across the entire range of allowed clock frequencies. Therefore it is important to select the correct supported crystal frequency as part of configuration or else it will always fail to start the oscillator.

    I have learned that selecting the correct supported crystal frequency is important as part of the bring up of the crystal, but it doesn't have an impact on the variation detection after the crystal has stabilized.

    There is a separate value that dictates that, which is also part of the MOSCCTL register. We've already discussed the CVAL and MOSCIM bits, and the other key one here is OSCRNG as this specifies the range for the Oscillator and that influences how the variation is being checked.

    Unfortunately, because this device was released many years ago (~2014), the design files are archived at this point and so we cannot check into the exact circuitry used for the variation detection and therefore can't provide a specific figure here.

    The next portion of this is only based on general knowledge about MCU designs to give some idea as to what to expect.

    Typically with these kind of architectures, the variance check is based on a broad range that is set by using an internal reference clock. For TM4C this would likely be the 16MHz PIOSC. And so the variation would use that as a basis and set a range higher and lower than the PIOSC to check for frequencies. So for example if the device is set to greater than 10 MHz, one possibility could be the range is PIOSC/2 < OSC < PIOSC*2 which would range from 8MHz to 32MHz and anything outside that range might trigger the failure. Again this is just an example for the sake of explaining what is likely being done by the device.

    Ultimately the point here is...

    Jason Reeder said:
    i.e. if the 25Mhz we’re using derives in 24Mhz, is there any failure alarm/flag that inform the uC about that variation?

    The variation detection is unlikely to detect that level of deviation in frequency in an MCU like this. 

    Best Regards,

    Ralph Jacobi

  • 0 in reply to Jason Reeder
    Guru 92251 points
    Jason Reeder said:
    i.e. if the 25Mhz we’re using derives in 24Mhz, is there any failure alarm/flag that inform the uC about that variation?

    Perhaps the software could compare the frequency of two clocks, one sourced by the MOSC and one by the PIOSC.

    The initialise_clock function in TM4C129_self_test.c is an example of where have used such a test before. The check isn't directly on the MOSC frequency, but on the CPU frequency for which MOSC in the input clock to the PLL.