Other Parts Discussed in Thread: HALCOGEN
Hello,
I am using the TMS570LC4357 and I am trying to reconcile the Safety Features and Diagnostics listed in the "Safety Manual for TMS570LC4x Hercules ARM Safety MCUs" (SPNU540A) with the ESM Channels described in the datasheet for the TMS570LC4357 Hercules (SPNS195C).
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Question 1
The "Safety Manual for TMS570LC4x Hercules ARM Safety MCUs" (SPNU540A) describes the following two safety features and diagnostics.
Primary Flash FLA2 Hard Error Cache and Livelock
Primary SRAM RAM2 Hard Error Cache and Livelock
Section 7.44 Flash Hard Error Cache and Livelock and section 7.104 Primary SRAM Hard Error Cache and Livelock both state that "Livelock is indicated via the ESM ... ".
The datasheet for the TMS570LC4357 Hercules (SPNS195C) section 6.19.2 ESM Channel Assignments lists the ESM error sources, their groups and channels in table 6-45.
It is not obvious to me which entry in the table corresponds to "Hard Error Cache and Livelock".
Can you tell me what ESM group and channel corresponds to "Hard Error Cache and Livelock"?
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Question 2
The "Safety Manual for TMS570LC4x Hercules ARM Safety MCUs" (SPNU540A) describes the following safety feature and diagnostic.
System Control Module SYS4 Multi-Bit Keyed Self-Correctable High-Integrity Bits
Section 7.150 states that this diagnostic is "signaled through the ESM".
Can you tell me which ESM group and channel corresponds to "Multi-Bit Keyed Self-Correctable High-Integrity Bits"?
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Question 3
The "Safety Manual for TMS570LC4x Hercules ARM Safety MCUs" (SPNU540A) describes the following safety feature and diagnostic.
Cortex-R5F Central Processing Unit (CPU) CPU12 ECC on Cache Memories
Table 4 states that this is an "ESM Error".
Can you tell me which ESM group and channel corresponds to CPU12 "ECC on Cache Memories"
Thank you.
